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VT82C596B
REVISION HISTORY
Document Release Revision 0.1 Date 2/23/99 Revision Initial release based on 82C596A Data Sheet revision 1.1 - Added UltraDMA-66 to feature bullets and overview - Added integrated APIC (changed H18, K18, J17 pin descriptions) - Added note to RTC CMOS Register Summary - Added / changed function 0 Rx42[6], Rx48[7-4], Rx5B[3], Rx5C[7-4, 2], Rx74[29-24, 8, 1], Rx87-89 - Added / changed function 3 Rx8, Rx4D[2-0], Rx54-55, Rx58-5B, Rx90-91, RxD2-D6 (80-88 renumbered), PMU I/O Offset 0[11], 20[14, 7-1], 22[14, 7-1], 24[14, 7-1], 28[15-11], 2A[15-11], 2C[11-10], 38[2-1], 44[10-1], 4C[30-0] Updated feature bullets, overview, and pin descriptions Replaced IDE function 1 with registers from 686B to reflect UltraDMA-66 Added / changed PMU function 3 registers Rx42[7-6, 4], Rx58-5B, PMU I/O Offset 0[8], 2C[2], 30[10-0], 34[10-0], 38[6, 4-3], 40 (removed) Changed Function 0 Rx42[2-0], 43[5-4], 50 default, 55[3-0], 57[3-0], 58[3-0], 88[5], Function 1 RxD, 42-43, 45[3-2], 54[4-3], 70, 74-75, 78, 7C-7D, Function 2 Rx41[7-3], Function 3 Rx4C-4F default value Initials DH
Revision 0.2
3/9/99
DH
Revision 0.3
6/17/99
DH
Revision 0.3 June 17, 1999
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Revision History
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VT82C596B
TABLE OF CONTENTS
REVISION HISTORY........................................................................................................................................................................I TABLE OF CONTENTS.................................................................................................................................................................. II LIST OF FIGURES..........................................................................................................................................................................IV LIST OF TABLES ...........................................................................................................................................................................IV OVERVIEW ....................................................................................................................................................................................... 3 PINOUTS ............................................................................................................................................................................................ 4 REGISTERS ..................................................................................................................................................................................... 21 REGISTER OVERVIEW ................................................................................................................................................................. 21 CONFIGURATION SPACE I/O ....................................................................................................................................................... 28 REGISTER DESCRIPTIONS............................................................................................................................................................ 29 Legacy I/O Ports ................................................................................................................................................................... 29
Keyboard Controller Registers.............................................................................................................................................................. 30 DMA Controller I/O Registers .............................................................................................................................................................. 32 Interrupt Controller Registers ............................................................................................................................................................... 33 Timer / Counter Registers ..................................................................................................................................................................... 33 CMOS / RTC Registers......................................................................................................................................................................... 34
Function 0 Registers - PCI to ISA Bridge........................................................................................................................... 35
PCI Configuration Space Header .......................................................................................................................................................... 35 ISA Bus Control.................................................................................................................................................................................... 36 Plug and Play Control ........................................................................................................................................................................... 39 Distributed DMA / Serial IRQ Control ................................................................................................................................................. 41 Miscellaneous / General Purpose I/O.................................................................................................................................................... 42
Function 1 Registers - Enhanced IDE Controller .............................................................................................................. 47
PCI Configuration Space Header .......................................................................................................................................................... 47 IDE-Controller-Specific Confiiguration Registers ................................................................................................................................ 49 IDE I/O Registers.................................................................................................................................................................................. 54
Function 2 Registers - Universal Serial Bus Controller..................................................................................................... 55
PCI Configuration Space Header .......................................................................................................................................................... 55 USB-Specific Configuration Registers.................................................................................................................................................. 56 USB I/O Registers................................................................................................................................................................................. 57
Function 3 Registers - Power Management and SMBus .................................................................................................. 58
PCI Configuration Space Header .......................................................................................................................................................... 58 Power Management-Specific PCI Configuration Registers .................................................................................................................. 59 System Management Bus-Specific Configuration Registers ................................................................................................................. 65 System Management Bus I/O-Space Registers...................................................................................................................................... 66 Power Management I/O-Space Registers .............................................................................................................................................. 70
FUNCTIONAL DESCRIPTIONS .................................................................................................................................................. 78 POWER MANAGEMENT................................................................................................................................................................ 78
Power Management Subsystem Overview ............................................................................................................................................ 78 Processor Bus States ............................................................................................................................................................................. 78 System Suspend States and Power Plane Control ................................................................................................................................. 79 General Purpose I/O Ports..................................................................................................................................................................... 79 Power Management Events ................................................................................................................................................................... 80 System and Processor Resume Events .................................................................................................................................................. 80 Legacy Power Management Timers ...................................................................................................................................................... 81 System Primary and Secondary Events ................................................................................................................................................. 81 Peripheral Events .................................................................................................................................................................................. 81
ELECTRICAL SPECIFICATIONS............................................................................................................................................... 82
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Table of Contents
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VT82C596B
ABSOLUTE MAXIMUM RATINGS ................................................................................................................................................. 82 DC CHARACTERISTICS................................................................................................................................................................ 82 AC TIMING SPECIFICATIONS ...................................................................................................................................................... 83 PACKAGE MECHANICAL SPECIFICATIONS ........................................................................................................................ 90
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Table of Contents
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VT82C596B
LIST OF FIGURES
FIGURE 1. PC SYSTEM CONFIGURATION USING THE VT82C596B ................................................................................. 3 FIGURE 2. VT82C596B BALL DIAGRAM (TOP VIEW)........................................................................................................... 4 FIGURE 3. VT82C596B PIN LIST (NUMERICAL ORDER)...................................................................................................... 5 FIGURE 4. VT82C596B PIN LIST (ALPHABETICAL ORDER)............................................................................................... 6 FIGURE 5. STRAP OPTION CIRCUIT....................................................................................................................................... 40 FIGURE 6. POWER MANAGEMENT SUBSYSTEM BLOCK DIAGRAM ........................................................................... 78 FIGURE 8. ULTRADMA-33 IDE TIMING - DRIVE INITIATING DMA BURST FOR READ COMMAND.................... 85 FIGURE 9. ULTRADMA-33 IDE TIMING - DRIVE INITIATING BURST FOR WRITE COMMAND............................ 85 FIGURE 10. ULTRADMA-33 IDE TIMING - PAUSING A DMA BURST ............................................................................. 86 FIGURE 11. ULTRADMA-33 IDE TIMING - DRIVE TERMINATING DMA BURST DURING READ COMMAND.... 87 FIGURE 12. ULTRADMA-33 IDE TIMING - DRIVE TERMINATING DMA BURST DURING WRITE COMMAND . 87 FIGURE 13. ULTRADMA-33 IDE TIMING - HOST TERMINATING DMA BURST DURING READ COMMAND...... 88 FIGURE 14. ULTRADMA-33 IDE TIMING - HOST TERMINATING DMA BURST DURING WRITE COMMAND ... 88 FIGURE 15. ULTRADMA-33 IDE TIMING - PIO CYCLE ...................................................................................................... 89 FIGURE 16. MECHANICAL SPECIFICATIONS - 324-PIN BALL GRID ARRAY PACKAGE ......................................... 90
LIST OF TABLES
TABLE 1. TABLE 2. TABLE 3. TABLE 4. TABLE 5. TABLE 6. TABLE 7. PIN DESCRIPTIONS..................................................................................................................................................... 7 SYSTEM I/O MAP ....................................................................................................................................................... 21 REGISTERS.................................................................................................................................................................. 21 KEYBOARD CONTROLLER COMMAND CODES .............................................................................................. 31 CMOS REGISTER SUMMARY................................................................................................................................. 34 AC CHARACTERISTICS - PCI CYCLE TIMING.................................................................................................. 83 AC CHARACTERISTICS - ULTRADMA-33 IDE BUS INTERFACE TIMING.................................................. 84
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Table of Contents
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VT82C596B
VT82C596B PIPC
PCI INTEGRATED PERIPHERAL CONTROLLER PC98 COMPLIANT PCI-TO-ISA BRIDGE WITH ACPI, ENHANCED POWER MANAGEMENT, SMBUS, APIC, DISTRIBUTED DMA, SERIAL IRQ, PLUG AND PLAY, ULTRADMA-33/66 MASTER MODE PCI-EIDE CONTROLLER, USB CONTROLLER, KEYBOARD CONTROLLER, AND RTC
* Inter-operable with VIA and other Host-to-PCI Bridges - Combine with VT82C598 (Apollo MVP3) for a complete 66 / 75 / 83 / 100MHz Socket-7 PCI / AGP / ISA system - Combine with VT82C693 (Apollo ProPlus) for a complete 66 / 100 MHz Socket-370 or Slot-1 PCI / ISA system - Combine with VT82C693A (Apollo Pro133) for a complete 66 / 100 / 133 MHz Skt-370 or Slot-1 PCI / ISA system * PC98 Compliant PCI to ISA Bridge - - - - - - - - - - - - - - - - * - - - - - * - - - -
Integrated ISA Bus Controller with integrated DMA, timer, and interrupt controller Integrated Keyboard Controller with PS2 mouse support Integrated DS12885-style Real Time Clock with extended 256 byte CMOS RAM and Day/Month Alarm for ACPI Integrated USB Controller with root hub and two function ports Integrated UltraDMA-33/66 master mode EIDE controller with enhanced PCI bus commands PCI-2.1 compliant with delay transaction Eight double-word line buffer between PCI and ISA bus One-level PCI to ISA post-write buffer Supports type F DMA transfers Distributed DMA support for ISA legacy DMA across the PCI bus Sideband signal support for PC/PCI and serial interrupt for docking and non-docking applications Serial Interrupt input Fast reset and Gate A20 operation Edge trigger or level-sensitive interrupts Flash EPROM, 2Mb EPROM and combined BIOS support Supports positive and subtractive decoding
Universal Serial Bus Controller
USB v.1.1 and Intel Universal HCI v.1.1 compatible Eighteen level (doublewords) data FIFO with full scatter / gather capabilities Root hub and two function ports Integrated physical layer transceivers with over-current detection status on USB inputs Legacy keyboard and PS/2 mouse support
Advanced Programmable Interrupt Controller (APIC)
Integrated on-chip Control pins provided for support of optional external APIC Used to extend system interrupt capability PC98 compliant
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Features
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VT82C596B
*
UltraDMA-33/66 Master Mode PCI EIDE Controller - - - - - - - - - - - -
Dual channel master mode PCI supporting four Enhanced IDE devices Transfer rate up to 22MB/sec to cover PIO mode 4, multi-word DMA mode 2 drives, and beyond Extension to UltraDMA-33 interface for transfer rates to 33MB/sec Extension to UltraDMA-66 interface for transfer rates to 66MB/sec Thirty-two levels (doublewords) of prefetch and write buffers Dual DMA engine for concurrent dual channel operation Bus master programming interface for SFF-8038i rev.1.0 and Windows-95 compliant Full scatter gather capability Support ATAPI compliant devices including DVD devices Support PCI native and ATA compatibility modes Complete software driver support Supports glue-less "Swap-Bay" option with full electrical isolation
*
System Management Bus Interface - Host interface for processor communications - Slave interface for external SMBus masters
*
Sophisticated PC98-Compatible Mobile Power Management - - - - - - - - - - - - - - - - - - - - -
Supports both ACPI (Advanced Configuration and Power Interface) and legacy (APM) power management ACPI v1.0 Compliant APM v1.2 Compliant CPU clock throttling and clock stop control for complete ACPI C0 to C3 state support PCI bus clock run and PCI/CPU clock generator stop control Supports multiple system suspend types: power-on suspends with flexible CPU/PCI bus reset options, suspend to DRAM, and suspend to disk (soft-off), all with hardware automatic wake-up Multiple suspend power plane controls and suspend status indicators One idle timer, one peripheral timer and one general purpose timer, plus 24/32-bit ACPI compliant timer Normal, doze, sleep, suspend and conserve modes Global and local device power control System event monitoring with two event classes Primary and secondary interrupt differentiation for individual channels Dedicated input pins for power and sleep buttons, external modem ring indicator, and notebook lid open/close for system wake-up Up to 22 general purpose input ports and 31 output ports Multiple internal and external SMI sources for flexible power management models Two programmable chip selects and one microcontroller chip select Enhanced integrated real time clock (RTC) with date alarm, month alarm, and century field Thermal alarm support Cache SRAM power-down control Hot docking support I/O pad leakage control
*
Plug and Play Controller - PCI interrupts steerable to any interrupt channel - Dual interrupt and DMA signal steering for on-board plug and play devices - Microsoft Windows 95TM and plug and play BIOS compliant
* * *
Built-in NAND-tree pin scan test capability 0.5u, 3.3V, low power CMOS process Single chip 324 pin BGA
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Features
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VT82C596B
OVERVIEW
The VT82C596B south bridge is a high integration, high performance, power-efficient, and high compatibility device that supports PCI / ISA bus bridge functionality to make a complete Microsoft PC98-compliant system. In addition to complete ISA extension bus functionality, the VT82C596B includes standard intelligent peripheral controllers: a) Master mode enhanced IDE controller with dual channel DMA engine and interlaced dual channel commands. Dedicated FIFO coupled with scatter and gather master mode operation allows high performance transfers between PCI and IDE devices. In addition to standard PIO and DMA mode operation, the VT82C596B also supports the UltraDMA-33 standard to allow reliable data transfer rates up to 33MB/sec throughput and the UltraDMA-66 standard for 66MB/sec data transfer. The IDE controller is SFF-8038i v1.0 and Microsoft Windows-95 / 98 / NT compliant. b) Universal Serial Bus controller that is USB v1.1 and Universal HCI v1.1 compliant. The VT82C596B includes the root hub with two function ports with integrated physical layer transceivers. The USB controller allows hot plug and play and isochronous peripherals to be inserted into the system with universal driver support. The controller also implements legacy keyboard and mouse support so that legacy software can run transparently in a non-USB-aware operating system environment. c) Keyboard controller with PS2 mouse support. d) Real Time Clock with 256 byte extended CMOS. In addition to the standard ISA RTC functionality, the integrated RTC also includes the date alarm, century field, and other enhancements for compatibility with the ACPI standard. e) Notebook-class power management functionality compliant with ACPI and legacy APM requirements. Multiple sleep states (power-on suspend, suspend-to-DRAM, and suspend-to-Disk) are supported with hardware automatic wake-up. Additional functionality includes event monitoring, CPU clock throttling and stop (Intel processor protocol), PCI bus clock stop control, modular power, clock and leakage control, hardware-based and software-based event handling, general purpose I/O, chip select and external SMI. f) Full System Management Bus (SMBus) interface. g) Distributed DMA capability for support of ISA legacy DMA over the PCI bus. PC/PCI and Serial IRQ mechanisms are also supported for docking and non-docking applications. h) Plug and Play controller that allows complete steerability of all PCI interrupts to any interrupt channel. Three additional steerable interrupt channels are provided to allow plug and play and reconfigurability of on-board peripherals for Windows 95 compliance. i) Integrated APIC (see the Win98 Hardware Design Guide) The VT82C596B also enhances the functionality of the standard ISA peripherals. The integrated interrupt controller supports both edge and level triggered interrupts channel by channel. The integrated DMA controller supports type F DMA in addition to standard ISA DMA modes. Compliant with the PCI-2.1 specification, the VT82C596B supports delayed transactions so that slower ISA peripherals do not block the traffic of the PCI bus. Special circuitry is built in to allow concurrent operation without causing dead lock even in a PCI-to-PCI bridge environment. The chip also includes eight levels (doublewords) of line buffers from the PCI bus to the ISA bus to further enhance overall system performance.
CPU / Cache Sideband Signals: Init / CPUreset IRQ / NMI SMI / StopClk FERR / IGNNE Boot ROM CA CD North Bridge MA/Command MD PCI I2C (Module ID) VT82C596B RTC Crystal 324 BGA USB Expansion KBC Cards IDE GPIO, Power Control, Reset ISA System Memory
Figure 1. PC System Configuration Using the VT82C596B
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Overview
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VT82C596B
PINOUTS
Figure 2. VT82C596B Ball Diagram (Top View)
Key A B C D E F G H J 1 PCI RST# AD 31 AD 30 AD 28 AD 29 USBP1+ 2 AD 27 AD 26 AD 25 CBE 3# AD 24 3 ID SEL AD 23 AD 22 AD 20 AD 21 4 AD 19 AD 18 AD 17 5 6 FRA ME# SERR# I RDY# PAR T CBE RDY# 1# AD 14 AD 15 7 AD 13 AD 12 AD 11 AD 10 GND 8 AD 9 AD 8 CBE 0# AD 6 AD 7 9 AD 5 AD 4 AD 3 AD 2 10 AD 1 AD 0 11 12 PCI P RQB# GNT# PCI P RQC# REQ# SD D7 SD D8 13 SD D6 SD D9 SD D5 SD D10 GND 14 SD D4 SD D11 SD D3 SD D2 SD D12 15 SD D13 SD D1 SD D14 SD D15 SD D0 16 17 SD SD DRQ DACK# SD IOW# SD IOR# SD RDY VCC SD A1 SD A0 PD D12 PD D14 18 SD A2 SD CS1# SD CS3# PD D3 PD D1 PD DRQ PD A1 19 PD D8 PD D9 PD D10 PD D11 PD D13 PD D15 PD 20 PD D7 PD D6 PD D5 PD D4 PD D2 PD D0 PD IRQ0 OUT IRQ 1
PCK PCI RUN# RQD# GND P CLK
CBE 2# STOP# AD 16 DEV SEL#
PCI VCC RQA# VCC VCC
GPO GPO29 GPO 28 SCI# 30 GPI 21 USB P0GPI 14 GPI 16 USB CLK X DIR# GPO 0 GPI 19
VCC VCC GPO 27 GPI 20 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC
VCC VCC
PD PD IOW# IOR# PD A0 PD A2
PIRQ USBD# P0+ GPI 18 USB P1-
DACK# RDY
PD PD ACS#/ TH CS3# CS1# APD0 RM# AAK#/ STP VREF APD1 CLK# ZZ V BAT NC SER IRQ
USB USB OC0# OC1#
NC / GND KEYL USB GPI 17 PCS 0# VCC USB GPI 15
KBCS# ROM K /MSDT CS#
ARQ#/ SPKR WSC# FERR# SLP# IGN NE# INIT INTR CPU RST RTC X1 GPI 1 SMB CLK NMI A20 M# RC IN# SMI# RTC X2
L M N
RTCALE REQ A# GNT A#
GPI 13 RTC CS#
X NC / OE# KBDT PCS 1# PIRQ C# NC SA 16 DRQ 3 DACK 3# SA 17 IOR# VCC VCC VCC DRQ 1 SA 14 B CLK SA 11 SA 12 SA 9 IRQ 5 IRQ 6 SA 10 IRQ 7
RSM PWR RST# GD NC RI# CFG 2 SUS ST2#
REQ NC / MC B# KBCK CS# REQ C# GNT C#
VCC SMB SUS ALRT# VCC VCC IRQ 3 SA 6 SA 7 IRQ 4 SA 8 SA 4 BALE TC SA 5 DACK 2# SA 1 SA 0 OSC SA 2 SA 3 LA 23 IRQ 10 IOCS 16# S BHE# MCS 16# IRQ 12 LA 20 LA 21 IRQ 11 LA 22 LA 18 LID VCC SUS SUS CLK CFG 1 SUS ST1# DRQ 7 SD 11 DACK 7# SD 10
A20G/ GNT P MSCK B# R T U V W CPU PCI STP# STP# SD 6 IRQ 9 SD 7 RST DRV SD 3 SD 2 DRQ 2 SD 4 SD 5
PIRQ PIRQ A# B# IOCH RDY IOW# SMEM W# SD 0 SD 1 SA 18 SA 19 SMEM R#
DACK SD9 5#
GPO SMB 8 DATA
DACK MEM DRQ 0# W# 6 IRQ 14 LA 19 IRQ 15 MEM DACK R# 6# DRQ 0 LA 17 SD 8 DRQ 5
SUS BAT PWR C# LOW# BTN# TEST# SD 13 SD 12 SUS B# SD 15 SD 14 EXT SMI# SUS A# IRQ 8#
DACK 1# RFSH# SA 15 SA 13
IO Y CHK#
ZWS# AEN
Note: Some of the pins above have alternate functions and alternate names. The table above contains only one name, but the pin lists and pin descriptions contain all names.
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Pinouts
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VT82C596B
Figure 3. VT82C596B Pin List (Numerical Order)
Pin A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 D01 D02 D03 D04 D05
O IO I IO IO I IO IO IO IO I I IO IO IO I O O IO IO IO IO IO IO IO O IO IO IO IO I O IO IO IO O O O IO IO IO IO IO IO IO IO IO IO IO IO I IO IO IO IO O O O IO IO IO IO IO IO IO
Pin Name PCIRST# AD27 IDSEL AD19 FRAME# SERR# AD13 AD9 AD5 AD1 PCIREQB# PGNT# SDD6 SDD4 SDD13 SDDRQ SDDACK# SDA2 PDD8 PDD7 AD31 AD26 AD23 AD18 IRDY# PAR AD12 AD8 AD4 AD0 PCIREQC# PREQ# SDD9 SDD11 SDD1 SDIOW# SDA1 SDCS1# PDD9 PDD6 AD30 AD25 AD22 AD17 TRDY# CBE1# AD11 CBE0# AD3 PCKRUN# PCIREQD# SDD7 SDD5 SDD3 SDD14 SDIOR# SDA0 SDCS3# PDD10 PDD5 AD28 CBE3# AD20 CBE2# STOP#
Pin Pin Name D06 IO AD14 D07 IO AD10 D08 IO AD6 D09 IO AD2 D10 P GND D11 I PCLK D12 IO SDD8 D13 IO SDD10 D14 IO SDD2 D15 IO SDD15 D16 I SDRDY D17 IO PDD12 D18 IO PDD3 D19 IO PDD11 D20 IO PDD4 E01 IO AD29 E02 IO AD24 E03 IO AD21 E04 IO AD16 E05 IO DEVSEL# E06 IO AD15 E07 P GND E08 IO AD7 E09 P VCC E10 I PCIREQA# E11 P VCC E12 P VCC E13 P GND E14 IO SDD12 E15 IO SDD0 E16 P VCC E17 IO PDD14 E18 IO PDD1 E19 IO PDD13 E20 IO PDD2 F01 IO USBP1+ F02 O GPO28 F03 O GPO29/SCI# F04 O GPO30 F05 P VCC F06 P VCC F14 P VCC F15 P VCC F16 O PDIOW# F17 O PDIOR# F18 I PDDRQ F19 IO PDD15 F20 IO PDD0 G01 IOD PIRQD# G02 IO USBP0+ G03 I GPI21 G04 O GPO0 G05 O GPO27 G06 P VCC G16 O PDA0 G17 O PDA2 G18 O PDA1 G19 O PDDACK# G20 I PDRDY H01 I GPI18 H02 IO USBP1H03 IO USBP0H04 I GPI19 H05 I GPI20 H16 O PDCS3#
Pin H17 H18 H19 H20 J01 J02 J03 J04 J05 J09 J10 J11 J12 J16 J17 J18 J19 J20 K01 K02 K03 K04 K05 K09 K10 K11 K12 K16 K17 K18 K19 K20 L01 L02 L03 L04 L05 L09 L10 L11 L12 L16 L17 L18 L19 L20 M01 M02 M03 M04 M05 M09 M10 M11 M12 M16 M17 M18 M19 M20 N01 N02 N03 N04 N05
O O I O I I I I P P P P P P O OD I I IO O I I P P P P P O O I I OD O I I O I P P P P P OD OD OD OD I O O O IO P P P P I I OD OD O I IO O O
Pin Name PDCS1# APICCS#/D0/GPO13 THRM# / GPI8 IRQ0OUT / GPO14 USBOC0# USBOC1# GPI14 NC / KEYLOCK GNDUSB GND GND GND GND VREF APICACK#/D1/GPO12 STPCLK# SERIRQ / GPI7 IRQ1 KBCS#/GPO26/MSDT ROMCS# GPI16 GPI17 VCCUSB GND GND GND GND ZZ / GPO19 SPKR APICRQ#/WSC#/GPI5 FERR# SLP# RTCAS / GPO25 GPI13 / SLPBTN# USBCLK PCS0# GPI15 GND GND GND GND VBAT IGNNE# INIT INTR NMI REQA# / GPI2 RTCCS# / GPO24 XDIR# / GPO22 XOE# / GPO23 NC / KBDT GND GND GND GND NC RSMRST# PWRGD CPURST A20M# GNTA# / GPO9 REQB# / GPI3 NC / KBCK MCCS# PCS1#
Pin N16 N17 N18 N19 N20 P01 P02 P03 P04 P05 P15 P16 P17 P18 P19 P20 R01 R02 R03 R04 R05 R06 R07 R15 R16 R17 R18 R19 R20 T01 T02 T03 T04 T05 T06 T07 T08 T09 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 U01 U02 U03 U04 U05 U06 U07 U08 U09 U10 U11 U12 U13 U14 U15 U16
P I I I IO O I O IOD P I O I I OD O O IOD IOD P P P P I I IO O IO IO IOD IO IO P O IO I IO IO IO I IO O IO O O O IO I IO O IO I I IO I IO O IO I IO O IO I
Pin Name VCCSUS SMBALRT# / GPI11 NC RTCX1 RCIN# A20GATE / MSCK GNTB# / GPO10 REQC# / GPI4 GNTC# / GPO11 PIRQC# VCC LID / GPI10 SUSCLK RI# / GPI12 GPI1 / PME# SMI# CPUSTP# / GPO17 PCISTP# / GPO18 PIRQA# PIRQB# NC VCC VCC VCC VCCSUS CFG1 CFG2 SMBCLK RTCX2 SD6 SD3 IOCHRDY IOW# SA16 VCC BCLK SA9 IRQ3 SA4 SA1 LA23 / GPO7 IRQ12 LA18 / GPO2 DACK5# SD9 SUSST1# / GPO20 SUSST2# / GPO21 GPO8 SMBDATA IRQ9 SD2 SMEMW# SA18 DRQ3 DRQ1 SA11 IRQ5 SA6 BALE SA0 IRQ10 LA20 / GPO4 DACK0# MEMW# DRQ6
Pin U17 U18 U19 U20 V01 V02 V03 V04 V05 V06 V07 V08 V09 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 W01 W02 W03 W04 W05 W06 W07 W08 W09 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 Y01 Y02 Y03 Y04 Y05 Y06 Y07 Y08 Y09 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20
I O I I IO I IO IO O IO IO I IO O I IO IO I IO O IO I O IOD O IO IO O IO O IO IO I IO IO IO I IO I IO O IO IO O I IO I O IO IO IO I IO O IO IO IO I IO I IO IO IO I
Pin Name DRQ7 SUSC# / GPO16 BATLOW# / GPI9 PWRBTN# SD7 DRQ2 SD0 SA19 DACK3# SA14 SA12 IRQ6 SA7 TC OSC IOCS16# LA21 IRQ14 MEMR# DACK6# SD11 TEST# SUSB# / GPO15 EXTSMI# RSTDRV SD4 SD1 SMEMR# SA17 DACK1# RFSH# SA10 IRQ4 SA5 SA2 SBHE# IRQ11 LA19 / GPO3 DRQ0 SD8 DACK7# SD13 SD15 SUSA# IOCHCK# / GPI0 SD5 ZWS# AEN IOR# SA15 SA13 IRQ7 SA8 DACK2# SA3 MCS16# LA22 / GPO6 IRQ15 LA17 / GPO1 DRQ5 SD10 SD12 SD14 IRQ8# / GPI6
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Pinouts
7HFKQRORJLHV ,QF
:H &RQQHFW
VT82C596B
Figure 4. VT82C596B Pin List (Alphabetical Order)
Pin Pin Name Pin Pin Name Pin Pin Name Pin Pin Name Pin Pin Name P01 IO A20GATE / MSCK K19 I FERR# K01 IO KBCS#/GPO26/MSDT M18 I PWRGD B13 IO SDD09 M20 OD A20M# A05 IO FRAME# Y15 IO LA17 / GPO1 N20 I RCIN# D13 IO SDD10 B10 IO AD00 T14 IO LA18 / GPO2 M01 I REQA# / GPI2 B14 IO SDD11 D10 P GND A10 IO AD01 W14 IO LA19 / GPO3 N02 I REQB# / GPI3 E14 IO SDD12 E07 P GND D09 IO AD02 U13 IO LA20 / GPO4 P03 I REQC# / GPI4 A15 IO SDD13 E13 P GND C09 IO AD03 V13 IO LA21 / GPO5 W07 IO RFSH# C15 IO SDD14 J09 P GND B09 IO AD04 Y13 IO LA22 / GPO6 P18 I RI# / GPI12 D15 IO SDD15 J10 P GND A09 IO AD05 T12 IO LA23 / GPO7 K02 O ROMCS# A17 O SDDACK# J11 P GND D08 IO AD06 P16 I LID / GPI10 M17 I RSMRST# A16 I SDDRQ J12 P GND E08 IO AD07 N04 O MCCS# W01 O RSTDRV C16 O SDIOR# K09 P GND B08 IO AD08 Y12 IO MCS16# L01 O RTCAS/GPO25 B16 O SDIOW# K10 P GND A08 IO AD09 V15 IO MEMR# M02 O RTCCS#/GPO24 J19 I SERIRQ / GPI7 K11 P GND D07 IO AD10 U15 IO MEMW# N19 I RTCX1 A06 I SERR# K12 P GND C07 IO AD11 J04 I NC / KEYLOCK R20 O RTCX2 D16 I SDRDY L09 P GND B07 IO AD12 M05 IO NC / KBDT U11 IO SA00 K20 OD SLP# L10 P GND A07 IO AD13 N03 IO NC / KBCK T11 IO SA01 N17 I SMBALRT#/GPI11 L11 P GND D06 IO AD14 M16 - NC W11 IO SA02 R19 IO SMBCLK L12 P GND E06 IO AD15 N18 - NC Y11 IO SA03 T20 IO SMBDATA M09 P GND E04 IO AD16 R05 - NC T10 IO SA04 W04 O SMEMR# M10 P GND C04 IO AD17 L20 OD NMI W10 IO SA05 U03 O SMEMW# M11 P GND B04 IO AD18 V11 I OSC U09 IO SA06 P20 OD SMI# M12 P GND A04 IO AD19 B06 O PAR V09 IO SA07 K17 O SPKR J05 P GNDUSB D03 IO AD20 N01 O GNTA# / GPO9 C10 IO PCKRUN# Y09 IO SA08 D05 IO STOP# E03 IO AD21 P02 O GNTB# / GPO10 D11 I PCLK T08 IO SA09 J18 OD STPCLK# C03 IO AD22 P04 O GNTC# / GPO11 E10 I PCIREQA# W08 IO SA10 W20 O SUSA# B03 IO AD23 P19 I GPI1 / PME# A11 I PCIREQB# U07 IO SA11 V19 O SUSB# / GPO15 E02 IO AD24 L02 I GPI13 / SLPBTN# B11 I PCIREQC# V07 IO SA12 U18 O SUSC# / GPO16 C02 IO AD25 J03 I GPI14 C11 I PCIREQD# Y07 IO SA13 P17 O SUSCLK B02 IO AD26 L05 I GPI15 A01 O PCIRST# V06 IO SA14 T17 O SUSST1# / GPO20 A02 IO AD27 K03 I GPI16 R02 O PCISTP#/GPO18 Y06 IO SA15 T18 O SUSST2# / GPO21 D01 IO AD28 K04 I GPI17 L04 O PCS0# T05 IO SA16 V10 O TC E01 IO AD29 H01 I GPI18 N05 O PCS1# W05 IO SA17 V18 I TEST# C01 IO AD30 H04 I GPI19 G16 O PDA0 U04 IO SA18 H19 I THRM# / GPI8 B01 IO AD31 H05 I GPI20 G18 O PDA1 V04 IO SA19 C05 IO TRDY# Y04 O AEN G03 I GPI21 G17 O PDA2 W12 IO SBHE# L03 I USBCLK J17 O APICAK#//D1/O12 G04 O GPO00 H17 O PDCS1# V03 IO SD00 J01 I USBOC0# H18 O APICCS#/D0/O13 T19 O GPO08 H16 O PDCS3# W03 IO SD01 J02 I USBOC1# K18 I APICRQ#/WSC#/I5 G05 O GPO27 F20 IO PDD00 U02 IO SD02 H03 IO USBP0U10 O BALE F02 O GPO28 E18 IO PDD01 T02 IO SD03 G02 IO USBP0+ U19 I BATLOW# / GPI9 F03 O GPO29 / SCIOUT# E20 IO PDD02 W02 IO SD04 H02 IO USBP1T07 O BCLK F04 O GPO30 D18 IO PDD03 Y02 IO SD05 F01 IO USBP1+ C08 IO CBE0# A03 I IDSEL D20 IO PDD04 T01 IO SD06 L16 P VBAT C06 IO CBE1# L17 OD IGNNE# C20 IO PDD05 V01 IO SD07 E09 P VCC D04 IO CBE2# L18 OD INIT B20 IO PDD06 W16 IO SD08 E11 P VCC D02 IO CBE3# L19 OD INTR A20 IO PDD07 T16 IO SD09 E12 P VCC R17 I CFG1 Y01 I IOCHCK# / GPI0 A19 IO PDD08 Y17 IO SD10 E16 P VCC R18 I CFG2 T03 IOD IOCHRDY B19 IO PDD09 V17 IO SD11 F05 P VCC M19 OD CPURST V12 IO IOCS16# C19 IO PDD10 Y18 IO SD12 F06 P VCC R01 O CPUSTP# / GPO17 Y05 IO IOR# D19 IO PDD11 W18 IO SD13 F14 P VCC U14 O DACK0# T04 IO IOW# D17 IO PDD12 Y19 IO SD14 F15 P VCC W06 O DACK1# B05 IO IRDY# E19 IO PDD13 W19 IO SD15 G06 P VCC Y10 O DACK2# H20 O IRQ0OUT / GPO14 E17 IO PDD14 C17 O SDA0 P15 P VCC V05 O DACK3# J20 I IRQ1 F19 IO PDD15 B17 O SDA1 R06 P VCC T15 O DACK5# T09 I IRQ3 G19 O PDDACK# A18 O SDA2 R07 P VCC V16 O DACK6# W09 I IRQ4 F18 I PDDRQ B18 O SDCS1# R15 P VCC W17 O DACK7# U08 I IRQ5 F17 O PDIOR# C18 O SDCS3# T06 P VCC E05 IO DEVSEL# V08 I IRQ6 F16 O PDIOW# E15 IO SDD00 N16 P VCCSUS W15 I DRQ0 Y08 I IRQ7 A12 I PGNT# B15 IO SDD01 R16 P VCCSUS U06 I DRQ1 Y20 I IRQ8# / GPI6 B12 O PREQ# D14 IO SDD02 K05 P VCCUSB V02 I DRQ2 U01 I IRQ9 G20 I PDRDY C14 IO SDD03 J16 P VREF U05 I DRQ3 U12 I IRQ10 R03 IOD PIRQA# A14 IO SDD04 M03 O XDIR# / GPO22 Y16 I DRQ5 W13 I IRQ11 R04 IOD PIRQB# C13 IO SDD05 M04 O XOE# / GPO23 U16 I DRQ6 T13 I IRQ12 P05 IOD PIRQC# A13 IO SDD06 Y03 I ZWS# U17 I DRQ7 V14 I IRQ14 G01 IOD PIRQD# C12 IO SDD07 K16 O ZZ / GPO19 V20 IOD EXTSMI# Y14 I IRQ15 U20 I PWRBTN# D12 IO SDD08 Referenced to VCCSUS: BATLOW#, CFG1-2, EXTSMI#, GPI1, GPO8, IRQ8#, LID, PWRBTN#, PWRGD, RI#, RSMRST#, SUSA-C#, SUSST1-2#, TEST#
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7HFKQRORJLHV ,QF
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VT82C596B
Table 1. Pin Descriptions
PCI Bus Interface
Signal Name PCLK FRAME# AD[31:0] Pin # D11 A5 B1, C1, E1, D1, A2, B2, C2, E2, B3, C3, E3, D3, A4, B4, C4, E4, E6, D6, A7, B7, C7, D7, A8, B8, E8, D8, A9, B9, C9, D9, A10, B10 D2, D4, C6, C8 B5 C5 D5 E5 B6 A6 I/O I IO IO Signal Description PCI Clock. PCLK provides timing for all transactions on the PCI Bus. Frame. Assertion indicates the address phase of a PCI transfer. Negation indicates that one more data transfer is desired by the cycle initiator. Address/Data Bus. The standard PCI address and data lines. The address is driven with FRAME# assertion and data is driven or received in following cycles.
C/BE[3:0]# IRDY# TRDY# STOP# DEVSEL# PAR SERR#
IO IO IO IO IO IO I
IDSEL PIRQA-D#
A3 R3, R4, P5, G1
I I
PREQ# PGNT# PCKRUN#
B12 A12 C10
O I IO
Command/Byte Enable. The command is driven with FRAME# assertion. Byte enables corresponding to supplied or requested data are driven on following clocks. Initiator Ready. Asserted when the initiator is ready for data transfer. Target Ready. Asserted when the target is ready for data transfer. Stop. Asserted by the target to request the master to stop the current transaction. Device Select. The VT82C596B asserts this signal to claim PCI transactions through positive or subtractive decoding. Parity. A single parity bit is provided over AD[31:0] and C/BE[3:0]#. System Error. SERR# can be pulsed active by any PCI device that detects a system error condition. Upon sampling SERR# active, the VT82C596B can be programmed to generate an NMI to the CPU. Initialization Device Select. IDSEL is used as a chip select during PCI configuration read and write cycles. PCI Interrupt Request. These pins are typically connected to the PCI bus INTA#INTD# pins as follows: PIRQC# PIRQD# PIRQA# PIRQB# PCI Slot 1 INTA# INTB# INTC# INTD# PCI Slot 2 INTB# INTC# INTD# INTA# PCI Slot 3 INTC# INTD# INTA# INTB# PCI Slot 4 INTD# INTA# INTB# INTC# PCI Request. This signal goes to the North Bridge to request the PCI bus. PCI Grant. This signal is driven by the North Bridge to grant PCI access to the VT82C596B. PCI Bus Clock Run. This signal indicates whether the PCI clock is or will be stopped (high) or running (low). The VT82C596B drives this signal low when the PCI clock is running (default on reset) and releases it when it stops the PCI clock. External devices may assert this signal low to request that the PCI clock be restarted or prevent it from stopping. Refer to the PCI Mobile Design Guide for more details.
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Pinouts
7HFKQRORJLHV ,QF
:H &RQQHFW
VT82C596B
CPU Interface
Signal Name CPURST INTR NMI
Pin # M19 L19 L20
I/O OD OD OD
Signal Description CPU Reset. The VT82C596B asserts CPURST to reset the CPU during power-up. CPU Interrupt. INTR is driven by the VT82C596B to signal the CPU that an interrupt request is pending and needs service. Non-Maskable Interrupt. NMI is used to force a non-maskable interrupt to the CPU. The VT82C596B generates an NMI when either SERR# or IOCHK# is asserted. Initialization. The VT82C596B asserts INIT if it detects a shut-down special cycle on the PCI bus or if a soft reset is initiated by the register Stop Clock. STPCLK# is asserted by the VT82C596B to the CPU in response to different Power-Management events. System Management Interrupt. SMI# is asserted by the VT82C596B to the CPU in response to different Power-Management events. Numerical Coprocessor Error. This signal is tied to the coprocessor error signal on the CPU. Internally generates interrupt 13 if active. Ignore Numeric Error. This pin is connected to the "ignore error" pin on the CPU. Sleep. Used to put the CPU to sleep. Used with slot-1 CPUs only. Not currently used with socket-7 CPUs.
INIT STPCLK# SMI# FERR# IGNNE# SLP#
L18 J18 P20 K19 L17 K20
OD OD OD I OD OD
Universal Serial Bus Interface
Signal Name USBP0+ USBP0USBOC0# USBP1+ USBP1USBOC1# USBCLK Pin # G2 H3 J1 F1 H2 J2 L3 I/O IO IO I IO IO I I Signal Description USB Port 0 Data + USB Port 0 Data USB Port 0 Over Current Detect. Port 0 is disabled if this input is low. USB Port 1 Data + USB Port 1 Data USB Port 1 Over Current Detect. Port 1 is disabled if this input is low. USB Clock. 48MHz clock input for Universal Serial Bus interface
System Management Bus (SMB) Interface (I2C Bus)
Signal Name SMBCLK SMBDATA SMBALRT# / GPI11 Pin # R19 T20 N17 I/O IO IO I Signal Description SMB / I2C Clock. SMB / I2C Data. MultiFunction Pin SMB Alert. (Rx74[5] = 0) When the chip is enabled to allow it, assertion generates an IRQ or SMI interrupt or a power management resume event. General Purpose Input 11. (Rx74[5] = 1) General purpose input.
Revision 0.3 June 17, 1999
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7HFKQRORJLHV ,QF
:H &RQQHFW
VT82C596B
UltraDMA-33 / 66 Enhanced IDE Interface
Signal Name PDRDY / PDDMARDY# / PDSTROBE
Pin # G20
I/O I
Signal Description EIDE Mode: Primary I/O Channel Ready. Device ready indicator UltraDMA Mode: Primary Device DMA Ready. Output flow control. The device may assert PDDMARDY# to pause output transfers Primary Device Strobe. Input data strobe (both edges). The device may stop PDSTROBE to pause input data transfers EIDE Mode: Secondary I/O Channel Ready. Device ready indicator UltraDMA Mode: Secondary Device DMA Ready. Output flow control. The device may assert SDDMARDY# to pause output transfers Secondary Device Strobe. Input data strobe (both edges). The device may stop SDSTROBE to pause input data transfers EIDE Mode: Primary Device I/O Read. Device read strobe UltraDMA Mode: Primary Host DMA Ready. Primary channel input flow control. The host may assert PHDMARDY# to pause input transfers Primary Host Strobe. Output data strobe (both edges). The host may stop PHSTROBE to pause output data transfers EIDE Mode: Secondary Device I/O Read. Device read strobe UltraDMA Mode: Secondary Host DMA Ready. Input flow control. The host may assert SHDMARDY# to pause input transfers Host Strobe B. Output strobe (both edges). The host may stop SHSTROBE to pause output data transfers EIDE Mode: Primary Device I/O Write. Device write strobe UltraDMA Mode: Primary Stop. Stop transfer: Asserted by the host prior to initiation of an UltraDMA burst; negated by the host before data is transferred in an UltraDMA burst. Assertion of STOP by the host during or after data transfer in UltraDMA mode signals the termination of the burst. EIDE Mode: Secondary Device I/O Write. Device write strobe UltraDMA Mode: Secondary Stop. Stop transfer: Asserted by the host prior to initiation of an UltraDMA burst; negated by the host before data is transferred in an UltraDMA burst. Assertion of STOP by the host during or after data transfer in UltraDMA mode signals the termination of the burst. Primary Device DMA Request. Primary channel DMA request Secondary Device DMA Request. Secondary channel DMA request Primary Device DMA Acknowledge. Primary channel DMA acknowledge Secondary Device DMA Acknowledge. Secondary channel DMA acknowledge
SDRDY / SDDMARDY# / SDSTROBE
D16
I
PDIOR# / PHDMARDY# / PHSTROBE
F17
O
SDIOR# / SHDMARDY# / SHSTROBE
C16
O
PDIOW# / PSTOP
F16
O
SDIOW# / SSTOP
B16
O
PDDRQ SDDRQ PDDACK# SDDACK#
F18 A16 G19 A17
I I O O
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VT82C596B
UltraDMA-33 / 66 Enhanced IDE Interface (continued)
Signal Name PDCS1# PDCS3# SDCS1# SDCS3# PDA[2-0] SDA[2-0] PDD[15-0]
Pin # H17 H16 B18 C18 G17, G18, G16 A18, B17, C17 F19, E17, E19, D17, D19, C19, B19, A19, A20, B20, C20, D20, D18, E20, E18, F20 D15, C15, A15, E14, B14, D13, B13, D12, C12, A13, C13, A14, C14, D14, B15, E15
I/O O O O O O O IO
Signal Description Primary Master Chip Select. This signal corresponds to CS1FX# on the primary IDE connector. Primary Slave Chip Select. This signal corresponds to CS3FX# on the primary IDE connector. Secondary Master Chip Select. This signal corresponds to CS17X# on the secondary IDE connector. Secondary Slave Chip Select. This signal corresponds to CS37X# on the secondary IDE connector. Primary Disk Address. PDA[2:0] are used to indicate which byte in either the ATA command block or control block is being accessed. Secondary Disk Address. SDA[2:0] are used to indicate which byte in either the ATA command block or control block is being accessed. Primary Disk Data
SDD[15-0]
IO
Secondary Disk Data
Revision 0.3 June 17, 1999
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Pinouts
7HFKQRORJLHV ,QF
:H &RQQHFW
VT82C596B
ISA Bus Interface
Signal Name SA[19:0]
Pin # V4, U4, W5, T5, Y6, V6, Y7, V7, U7, W8, T8, Y9, V9, U9, W10, T10, Y11, W11, T11, U11 T12, Y13, V13, U13, W14, T14, Y15 W19, Y19, W18, Y18, V17, Y17, T16, W16, V1, T1, Y2, W2, T2, U2, W3, V3 W12
I/O IO
Signal Description ISA Address Bus
LA[23:17]
IO
SD[15:0]
IO
ISA "Latched" Address Bus: The LA[23:17] address lines are bi-directional. These address lines allow accesses to physical memory on the ISA bus up to 16Mbytes. ISA Bus Data. SD[15:0] provide the data path for devices residing on the ISA bus. SD7:4 are strap options for keyboard inputs 6:3 (see Function 0 Rx5A)
SBHE#
IO
IOR# IOW# MEMR# MEMW# SMEMR# SMEMW# BALE
Y5 T4 V15 U15 W4 U3 U10
IO IO IO IO O O O
IOCS16# MCS16# IOCHCK# IOCHRDY
V12 Y12 Y1 T3
IO IO I IOD
ZWS#
Y3
I
ISA Byte High Enable. SBHE# indicates, when asserted, that a byte is being transferred on the upper byte (SD[15:8]) of the data bus. SBHE# is negated during refresh cycles. ISA I/O Read. IOR# is the command to an ISA I/O slave device which indicates that the slave may drive data on to the ISA data bus. ISA I/O Write. IOW# is the command to an ISA I/O slave device which indicates that the slave may latch data from the ISA data bus. ISA Memory Read. MEMR# is the command to a memory slave which indicates that it may drive data onto the ISA data bus. ISA Memory Write. MEMW# is the command to a memory slave which indicates that it may latch data from the ISA data bus. ISA Standard Memory Read. SMEMR# is the command to a memory slave, under 1MB, which indicates that it may drive data onto the ISA data bus ISA Standard Memory Write. SMEMW# is the command to a memory slave, under 1MB, which indicates that it may latch data from the ISA data bus. ISA Bus Address Latch Enable. BALE is an active high signal asserted by the VT82C596B to indicate that the address (SA[19:0], LA[23:17] and the SBHE# signal) is valid ISA 16-Bit I/O Chip Select. This signal is driven by I/O devices on the ISA Bus to indicate that they support 16-bit I/O bus cycles. ISA Memory Chip Select 16. ISA slaves that are 16-bit memory devices drive this line low to indicate they support 16-bit memory bus cycles. ISA I/O Channel Check. When this signal is asserted, it indicates that a parity or an uncorrectable error has occurred for a device or memory on the ISA Bus. ISA I/O Channel Ready. This signal is normally high. Devices on the ISA Bus assert IOCHRDY low to indicate that additional time (wait states) is required to complete the cycle. ISA Zero Wait State. Devices on the ISA Bus assert ZWS# to indicate that no wait states are required.
Revision 0.3 June 17, 1999
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Pinouts
7HFKQRORJLHV ,QF
:H &RQQHFW
VT82C596B
ISA Bus Interface (continued)
Signal Name RFSH# AEN IRQ0OUT / GPO14
Pin # W7 Y4 H20
I/O IO O O
Signal Description Refresh. As an output RFSH# indicates when a refresh cycle is in progress. As an input RFSH# is driven by 16-bit ISA Bus masters to indicate refresh cycle. Address Enable. AEN is asserted during DMA cycles to prevent I/O slaves from misinterpreting DMA cycles as valid I/O cycles. Multifunction Pin Rx74[7] = 1 Interrupt Request 0 Output. Reflects the state of the internal system timer IRQ0 signal. Rx74[7] = 0 General Purpose Output 14. Interrupt Request 1. Interrupt Request 3. Interrupt Request 4. Interrupt Request 5. Interrupt Request 6. Interrupt Request 7. Multifunction Pin Rx5A[2] = 0 Internal RTC disabled. Interrupt Request 8 from external RTC Rx5A[2] = 1 Internal RTC enabled. General Purpose Input 6. Interrupt Request 9. Interrupt Request 10. Interrupt Request 11. Interrupt Request 12. Interrupt Request 14. Interrupt Request 15. DMA Request. Used to request DMA services from the internal DMA controller.
IRQ1 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8# / GPI6
J20 T9 W9 U8 V8 Y8 Y20
I I I I I I I
IRQ9 IRQ10 IRQ11 IRQ12 IRQ14 IRQ15 DRQ7-5, 3-0
DACK7-5, 3-0#
TC SPKR
U1 U12 W13 T13 V14 Y14 U17, U16, Y16, U5, V2, U6, W15 W17, V16, T15, V5, Y10, W6, U14 V10 K17
I I I I I I I
O
Acknowledge. Used by the internal DMA controller to indicate that a request for DMA service has been granted. Terminal Count. Asserted to DMA slaves as a terminal count indicator. Speaker Drive. The output of internal timer/counter 2.
O O
Revision 0.3 June 17, 1999
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Pinouts
7HFKQRORJLHV ,QF
:H &RQQHFW
VT82C596B
XD Interface
Signal Name XDIR# / GPO22
Pin # M3
I/O O
Signal Description MultiFunction Pin X-Bus Data Direction. (Rx75[6]=0) Asserted low for all I/O read cycles and for memory read cycles to the programmed BIOS or APIC address space. XDIR# is tied directly to the direction control of a 74F245 transceiver that buffers the X-Bus data and ISA-Bus data. SD0-7 connect to the "A" side of the transceiver and XD0-7 connect to the "B" side. XDIR# high indicates that SD0-7 drives XD0-7. General Purpose Output 22. (Rx75[6]=1) General purpose output. MultiFunction Pin X-Bus Output Enable. (Rx75[6]=0) Asserted low for all decoded X-Bus cycles. XOE# is tied directly to the output enable of a 74F245 transceiver that buffers the X-Bus data and ISA-Bus data (see XDIR# above). General Purpose Output 23. (Rx75[6]=1) General purpose output. MultiFunction Pin External Keyboard Controller Chip Select. (Rx76[2] = 0) Asserted during read or write accesses to I/O ports 60h and 64h. General Purpose Output 26. (Rx76[2]=1) General purpose output. ROM Chip Select. Chip Select to the BIOS ROM. Microcontroller Chip Select. Asserted during read or write accesses to I/O ports 62h or 66h. Programmable Chip Selects. Asserted during I/O cycles to programmable read or write ISA address ranges. Devices selected by these pins are assumed to be on the XBus (XDIR# and XOE# are enabled).
XOE# / GPO23
M4
O
KBCS# / GPO26
K1
O
ROMCS# MCCS# PCS[1-0]#
K2 N4 N5, L4
O O O
Revision 0.3 June 17, 1999
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Pinouts
7HFKQRORJLHV ,QF
:H &RQQHFW
VT82C596B
Internal Real Time Clock
Signal Name RTCX1 RTCX2 RTCCS# / GPO24
Pin # N19 R20 M2
I/O I O O
Signal Description RTC Crystal Input: 32.768 KHz crystal or oscillator input. RTC Crystal Output: 32.768 KHz crystal output MultiFunction Pin External RTC Chip Select. (Rx76[0] = 0) Asserted for read or write accesses to RTC port 71h. Externally connected to a pair of OR gates (to logically AND the chip select with IOR# and IOW#) to generate the active-low RTC read and write commands. General Purpose Output 24. (Rx76[0] = 1) General purpose output. MultiFunction Pin External RTC Address Strobe. (Rx76[1] = 0) Asserted for writes to RTC I/O Port 70h. General Purpose Output 25. (Rx76[1] = 1) General purpose output.
RTCAS / GPO25
L1
O
Internal Keyboard Controller
Signal Name KEYLOCK / PIRQ1 Pin # J4 I/O I Signal Description Extended Function (PIIX4 PIRQ1) Rx59[1]=1 Key Lock. Input to internal keyboard controller Extended Function (PIIX4 No Connect) Rx5A[0]=1 (Internal keyboard controller enabled -strapped from XD0) Keyboard Clock Extended Function (PIIX4 No Connect) Rx5A[0]=1 (Internal keyboard controller enabled -strapped from XD0) Keyboard Data MultiFunction Pin Rx5A[1]=0 (internal keyboard controller disabled - strapped from XD1) Gate A20. From optional external keyboard controller Rx5A[1]=1 (internal keyboard controller enabled -strapped from XD1) Mouse Clock. Mouse clock (extended function not available on PIIX4) MultiFunction Pin Rx5A[1]=0 (Internal keyboard controller disabled -strapped from XD1) Keyboard Controller Chip Select. (Rx76[2]=0 external keyboard controller enabled) Chip select for external keyboard controller. General Purpose Output 26 (Rx76[2]=1 external keyboard controller disabled) General purpose output Rx5A[1]=1 (Internal keyboard controller enabled -strapped from XD1) Mouse Data. Mouse data (extended function not available on PIIX4)
KBCK / NC
N3
IO
KBDT / NC
M5
IO
MSCK / A20GATE
P1
IO
MSDT / KBCS# / GPO26
K1
IO
Revision 0.3 June 17, 1999
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Pinouts
7HFKQRORJLHV ,QF
:H &RQQHFW
VT82C596B
PC/PCI and Serial IRQ Control
Signal Name REQ[A-C]# / GPI[2-4] GNT[A-C]# / GPO[9-11] SERIRQ / GPI7
Pin # M1, N2, P3 N1, P2, P4 J19
I/O I O I
Signal Description PC/PCI DMA Requests. Used by PCI agent to request DMA services per the PC/PCI protocol. For GPI functions refer to Rx7D[2-0]. PC/PCI DMA Grants. Used to acknowledge DMA services per the PC/PCI protocol. For GPO functions refer to Rx7D[2-0]. Serial Interrupt Request. Used with Distributed DMA. For GPI see Rx68[3].
A20 Control
Signal Name A20GATE / MSCK Pin # P1 I/O I Signal Description Gate A20: Gate A20 output from optional external keyboard controller if used. Logically combined with Port 92 bit-1 (Fast_A20) and output on the A20M# signal. If the internal keyboard / PS2 mouse controller is used, this pin becomes the mouse clock input (the A20GATE signal comes directly from the internal keyboard controller). A20 Mask. Connect to A20 mask input of the CPU.
A20M#
M20
OD
APIC Interface
Signal Name APICREQ# / WSC# / GPI5 Pin # K18 I/O I/I/I Signal Description MultiFunction Pin Internal APIC Write Snoop Complete. (Rx74[7]=1 & Rx74[1]=1) Asserted by the north bridge to indicate that all snoop activity on the CPU bus initiated by the last PCI-to-DRAM write is complete and that it is safe to perform an APIC interrupt. External APIC Request. (Rx74[7]=1 & Rx74[1]=0) Asserted by external APIC synchronous to PCICLK prior to sending an interrupt over the APIC serial bus. This signals the VT82C596B to flush its internal buffers. General Purpose Input 5. (Rx74[7] = 0) MultiFunction Pin Internal APIC Data 0. (Rx74[7]=1 & Rx74[1]=1) External APIC Chip Select. (Rx74[7]=1 & Rx74[1]=0) The VT82C596B drives this signal active to select an external APIC (if used). This occurs if the external APIC is enabled and a PCI cycle is detected within the programmed APIC address range. General Purpose Output 13. (Rx74[7] = 0) MultiFunction Pin Internal APIC Data 1. (Rx74[7]=1 & Rx74[1]=1) External APIC Acknowledge. (Rx74[7]=1 & Rx74[1]=0) Asserted by the VT82C596B to indicate that it internal buffers have been flushed (in response to APICREQ#). This indicates to the external APIC that the VT82C596B's internal buffers have been flushed and that it is OK for the APIC to send its interrupt. General Purpose Output 12. (Rx74[7] = 0)
APICCS# / APICD0 / GPO13
H18
O/O/O
APICACK# / APICD1 / GPO12
J17
O/O/O
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VT82C596B
General Purpose Inputs
Signal Name GPI0 / IOCHCK# GPI1 / PME# GPI2 / REQA# GPI3 / REQB# GPI4 / REQC# GPI5 / APICREQ# GPI6 / IRQ8# GPI7 / SERIRQ GPI8 / THRM# GPI9 / BATLOW# GPI10 / LID GPI11 / SMBALRT# GPI12 / RI# GPI13 / SLPBTN#
Pin # Y1 P19 M1 N2 P3 K18 Y20 J19 H19 U19 P16 N17 P18 L2
I/O I I I I I I I I I I I I I I
Signal Description
General Purpose Input 0. (Rx74[0] = 0) General Purpose Input 1. General Purpose Input 2. (Rx7D[0] = 0) General Purpose Input 3. (Rx7D[1] = 0) General Purpose Input 4. (Rx7D[2] = 0) General Purpose Input 5. (Rx74[7] = 0) General Purpose Input 6. (Rx5A[2] = 1) General Purpose Input 7. (Rx68[3] = 0) General Purpose Input 8. (Rx74[2] = 1) General Purpose Input 9. (Rx74[3] = 1) General Purpose Input 10. (Rx74[4] = 1) General Purpose Input 11. (Rx74[5] = 1) General Purpose Input 12. (Rx74[6] = 1) General Purpose Input 13. Also functions as the ACPI sleep button if bit-9 of register 0 of ACPI I/O Space (Function 3) is enabled J3 I GPI14 General Purpose Input 14. L5 I GPI15 General Purpose Input 15. K3 I GPI16 General Purpose Input 16. K4 I GPI17 General Purpose Input 17. H1 I GPI18 General Purpose Input 18. H4 I GPI19 General Purpose Input 19. H5 I GPI20 / PIRQ0 General Purpose Input 20. (Rx59[0] = 1) See also Rx55[3:0] G3 I GPI21 / PIRQ2 General Purpose Input 21. (Rx59[2] = 1) See also Rx58[3:0] The underlined name above indicates the default function on power up.
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VT82C596B
General Purpose Outputs
Signal Name
Pin #
I/O
Signal Description
G4 O GPO0 General Purpose Output 0. Y15 GPO1 / LA17 IO General Purpose Output 1. Rx74[0] = 0. T14 GPO2 / LA18 IO General Purpose Output 2. Rx74[0] = 0. W14 GPO3 / LA19 IO General Purpose Output 3. Rx74[0] = 0. U13 GPO4 / LA20 IO General Purpose Output 4. Rx74[0] = 0. V13 GPO5 / LA21 IO General Purpose Output 5. Rx74[0] = 0. Y13 GPO6 / LA22 IO General Purpose Output 6. Rx74[0] = 0. T12 GPO7 / LA23 IO General Purpose Output 7. Rx74[0] = 0. T19 O GPO8 General Purpose Output 8. F3Rx54[1-0]. Optional 1Hz / 2Hz / 4Hz clock output N1 O GPO9 / GNTA# General Purpose Output 9. Rx7D[0] = 0. P2 O GPO10 / GNTB# General Purpose Output 10. Rx7D[1] = 0. P4 O GPO11 / GNTC# General Purpose Output 11. Rx7D[2] = 0. J17 O GPO12 / APICACK# General Purpose Output 12. Rx74[7] = 0. H18 O GPO13 / APICCS# General Purpose Output 13. Rx74[7] = 0. H20 O GPO14 / IRQ0OUT General Purpose Output 14. Rx74[7] = 0. V19 O GPO15 / SUSB# General Purpose Output 15. Rx75[0] = 1. See also F3Rx54[3]. U18 O GPO16 / SUSC# General Purpose Output 16. Rx75[0] = 1. See also F3Rx54[2]. R1 O GPO17 / CPUSTP# General Purpose Output 17. Rx75[1] = 1. R2 O GPO18 / PCISTP# General Purpose Output 18. Rx75[2] = 1. K16 O GPO19 / ZZ General Purpose Output 19. Rx75[3] = 1. T17 O GPO20 / SUSST1# General Purpose Output 20. Rx75[4] = 1. See also F3Rx54[4]. T18 O GPO21 / SUSST2# General Purpose Output 21. Rx75[5] = 1. See also F3Rx54[7]. M3 O GPO22 / XDIR# General Purpose Output 22. Rx75[6] = 1. M4 O GPO23 / XOE# General Purpose Output 23. Rx75[6] = 1. M2 O GPO24 / RTCCS# General Purpose Output 24. Rx76[0] = 1. L1 O GPO25 / RTCAS General Purpose Output 25. Rx76[1] = 1. K1 O GPO26 / KBCS# General Purpose Output 26. Rx76[2] = 1. G5 O GPO27 General Purpose Output 27. F2 O GPO28 General Purpose Output 28. F3 O GPO29 / SCIOUT# General Purpose Output 29. Rx74[7] = 0. F4 O GPO30 General Purpose Output 30. The underlined name above indicates the default function on power up.
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VT82C596B
Power Management
Signal Name PWRBTN#
Pin # U20
I/O I
Signal Description Power Button. Used by the Power Management subsystem to monitor an external system on/off button or switch. The VT82C596B performs a 200us debounce of this input if Rx40[5] is set to 1. This input is referenced to VCCSUS. ACPI Sleep Button. General purpose input 13, but also functions as the ACPI sleep button if bit-9 of register 0 of ACPI I/O Space (Function 3) is enabled. Reset CPU. This signal from an optional external keyboard controller (if used) causes an INIT signal to be generated to the CPU. Resume Reset. Resets the internal logic connected to the VCCSUS power plane and also resets portions of the internal RTC logic. External System Management Interrupt. When enabled to allow it, a falling edge on this input causes an SMI# to be generated to the CPU to enter SMI mode. Once asserted, this pin should be held low for at least four PCICLKs. The VT82C596B also asserts EXTSMI# in response to SMI# being activated within the Serial IRQ function. This pin should be connected to an external pullup. Power Management PCI Requests. Used by internal power management to monitor PCI requests for use of the PCI bus.
SLPBTN# / GPI13 RCIN# RSMRST# EXTSMI#
L2 N20 M17 V20
I I I IOD
PCIREQ[A-D]#
E10, A11, B11, C11
I
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VT82C596B
Power Management (continued)
Signal Name LID / GPI10
Pin # P16
I/O I
Signal Description Notebook Computer Display Lid Open / Closed Monitor. Used by the Power Management subsystem to monitor the opening and closing of the display lid of notebook computers. Can be used to detect either low-to-high and/or high-to-low transitions to generate an SMI#. The VT82C596B performs a 200 usec debounce of this input if Rx40[5] is set to 1. May optionally be programmed as a general purpose input (Rx74[4]=1). Ring Indicator. May be connected to external modem circuitry to allow the system to be re-activated by a received phone call. This input is referenced to VCCSUS. May optionally be programmed as a general purpose input (Rx74[6]=1). Thermal Detect. If the VT82C596B is enabled to allow it, asserting this signal initiates hardware Clock Throttling mode. This causes STPCLK# to be cycled at a preset programmable rate (see Function 3 configuration space Rx4C). May optionally be programmed as a general purpose input (Rx74[2]=1). ACPI System Control Interrupt. Connected to the external APIC if used. May optionally be programmed as a general purpose output (Rx74[7]=0). CPU Clock Stop. Signals the system clock generator to disable the CPU clock outputs. May optionally be programmed as a general purpose output (Rx75[1]=1). PCI Clock Stop. Signals the system clock generator to disable the PCI clock outputs. May optionally be programmed as a general purpose output (Rx75[2]=1). L2 Cache SRAM Low Power Mode. Used to power down the L2 Cache SRAMs during CPU Stop Clock state. May optionally be programmed as a general purpose output (Rx75[3]=1). Suspend Plane A Control. Asserted during power management POS, STR, and STD suspend states. Used to control the primary power plane. Suspend Plane B Control. Asserted during power management STR and STD suspend states. Used to control the secondary power plane. May optionally be programmed as a general purpose output (Rx75[0]=1). Suspend Plane C Control. Asserted during power management STD suspend state. Used to control the tertiary power plane. May optionally be programmed as a general purpose output (Rx75[0]=1). Suspend Status 1. Typically connected to the North Bridge (e.g., VT82C598 Apollo MVP3) to provide information on host clock status. Asserted when the system may stop the host clock, such as Stop Clock or during POS, STR, or STD suspend states. May optionally be programmed as a general purpose output (Rx75[4]=1). Suspend Status 2. Typically connected to other system devices to provide information on system suspend state. Asserted during POS, STR, or STD suspend states. May optionally be programmed as a general purpose output (Rx75[5]=1).
RI# / GPI12
P18
I
THRM# / GPI8
H19
I
SCIOUT# / GPO29 CPUSTP# / GPO17
F3 R1
O O
PCISTP# / GPO18
R2
O
ZZ / GPO19
K16
O
SUSA# SUSB# / GPO15
W20 V19
O O
SUSC# / GPO16
U18
O
SUSST1# / GPO20
T17
O
SUSST2# / GPO21
T18
O
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VT82C596B
Resets and Clocks
Signal Name PWRGD PCIRST# RSTDRV BCLK OSC SUSCLK
Pin # M18 A1 W1 T7 V11 P17
I/O I O O O I O
Signal Description Power Good. Connected to the PWRGOOD signal on the Power Supply. PCI Reset. Active low reset signal for the PCI bus. The VT82C596B will assert this pin during power-up or from the control register. Reset Drive. Reset signal to the ISA bus. Bus Clock. ISA bus clock. Oscillator. 14.31818 MHz clock signal used by the internal Timer. Suspend Clock. 32.768 KHz output clock for use by the North Bridge (e.g., VT82C598 Apollo MVP3) for DRAM refresh purposes. Stopped during Suspend-toDisk and Soft-Off modes.
Configuration and Test
Signal Name CFG1 CFG2 TEST# Pin # R17 R18 V18 I/O I I I Signal Description Configuration 1. Used to select the CPU type (0=Socket-7, 1=Slot-1). Determines the polarity of the INIT and CPURST signals. Configuration 2. Used to select the type of decoding for the top 64 Kbytes of memory (FFFF0000h-FFFFFFFFh): 0 = Positive decode, 1 = Subtractive decode. Test. Used to select chip test modes. Pulled up externally to VCCSUS for normal operation.
Power and Ground
Signal Name VCC Pin # E9, E11, E12, E16, F5, F6, F14, F15, G6, P15, R6, R7, R15, T6 J16 I/O P Signal Description Core Power. 3.3V nominal (3.15V to 3.45V). This supply is turned on only when the mechanical switch on the power supply is turned on and the PWRON signal is conditioned high. This pin should be connected to the same voltage as the CPU I/O circuitry. Voltage Reference. 5V nominal (4.75 to 5.25) to provide 5V input tolerance. This voltage should be on only when the mechanical switch on the power supply is turned on and the PWRON signal is conditioned high. Suspend Power. Always available unless the mechanical switch of the power supply is turned off. If the "soft-off" state is not implemented, then this pin can be connected to VCC. Signals powered by or referenced to this plane are: BATLOW#, CFG1-2, EXTSMI#, GPI1, GPO8, IRQ8#, LID, RI#, SMBALRT#, SMBCLK, SMBDATA, PWRBTN#, SUS[A-C]#, SUSCLK, SUSST[1-2]#, TEST#, PWROK, RSMRST#. RTC Battery. Battery input for internal RTC (RTCX1, RTCX2) USB Differential Output Power Source (USBP0+, P0-, P1+, P1-) USB Differential Output Ground Ground
VREF
P
VCCSUS
N16, R16
P
VBAT VCCUSB GNDUSB GND
NC
L16 K5 J5 D10, E7, E13, J9-12, K9-12, L9-12, M9-12 J4, M5, M16, N3, N18, R5
P P P P
-
No Connect
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VT82C596B
Table 3. Registers
Legacy I/O Registers
REGISTERS
Register Overview
The following tables summarize the configuration and I/O registers of the VT82C596B. These tables also document the power-on default value ("Default") and access type ("Acc") for each register. Access type definitions used are RW (Read/Write), RO (Read/Only), "--" for reserved / used (essentially the same as RO), and RWC (or just WC) (Read / Write 1's to Clear individual bits). Registers indicated as RW may have some read/only bits that always read back a fixed value (usually 0 if unused); registers designated as RWC or WC may have some read-only or read write bits (see individual register descriptions for details). Detailed register descriptions are provided in the following section of this document. All offset and default values are shown in hexadecimal unless otherwise indicated Port 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
Table 2. System I/O Map
Port 00-1F 20-3F 40-5F 60-6F (60h) (61h) (64h) 70-77 78-7F 80 81-8F 90-91 92 93-9F A0-BF C0-DF E0-FF 100-CF7 Function Master DMA Controller Timer / Counter Actual Port Decoding 0000 0000 000x nnnn 0000 0000 010x xxnn
Master DMA Controller Registers Channel 0 Base & Current Address Channel 0 Base & Current Count Channel 1 Base & Current Address Channel 1 Base & Current Count Channel 2 Base & Current Address Channel 2 Base & Current Count Channel 3 Base & Current Address Channel 3 Base & Current Count Status / Command Write Request Write Single Mask Write Mode Clear Byte Pointer FF Master Clear Clear Mask Read / Write Mask
Default Acc RW RW RW RW RW RW RW RW RW WO WO WO WO WO WO RW Default Acc -- * -- * -- RW -- RW
Master Interrupt Controller 0000 0000 001x xxxn Keyboard Controller 0000 0000 0110 xnxn KBC Data 0000 0000 0110 x0x0 Misc Functions & Spkr Ctrl 0000 0000 0110 xxx1 KBC Command / Status 0000 0000 0110 x1x0 RTC/CMOS/NMI-Disable 0000 0000 0111 0nnn -available for system use- 0000 0000 0111 1xxx -reserved- (debug port) DMA Page Registers -available for system useSystem Control -available for system useSlave Interrupt Controller Slave DMA Controller -available for system use-available for system use0000 0000 1000 0000 0000 0000 1000 nnnn 0000 0000 1001 000x 0000 0000 1001 0010 0000 0000 1001 nnnn 0000 0000 101x xxxn 0000 0000 110n nnnx 0000 0000 111x xxxx
Port Master Interrupt Controller Regs 20 Master Interrupt Control 21 Master Interrupt Mask 20 Master Interrupt Control Shadow 21 Master Interrupt Mask Shadow * RW if shadow registers are disabled Port 40 41 42 43 Port 60 61 64 Timer/Counter Registers Timer / Counter 0 Count Timer / Counter 1 Count Timer / Counter 2 Count Timer / Counter Control Keyboard Controller Registers Keyboard Controller Data Misc Functions & Speaker Control Keyboard Ctrlr Command / Status
Default Acc RW RW RW WO Default Acc RW RW RW
CF8-CFB PCI Configuration Address 0000 1100 1111 10xx CFC-CFF PCI Configuration Data 0000 1100 1111 11xx D00-FFFF -available for system use-
Port CMOS / RTC / NMI Registers Default Acc 70 CMOS Memory Address & NMI Disa WO 71 CMOS Memory Data (128 bytes) RW 72 CMOS Memory Address RW 73 CMOS Memory Data (256 bytes) RW 74 CMOS Memory Address RW 75 CMOS Memory Data (256 bytes) RW NMI Disable is port 70h (CMOS Memory Address) bit-7. RTC control occurs via specific CMOS data locations (0-0Dh). Ports 72-73 may be used to access all 256 locations of CMOS. Ports 74-75 may be used to access CMOS if the internal RTC is disabled.
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Register Overview
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VT82C596B
Default Acc RW RW RW RW RW RW RW RW Default Acc RW Port C0 C2 C4 C6 C8 CA CC CE D0 D2 D4 D6 D8 DA DC DE Slave DMA Controller Registers Channel 0 Base & Current Address Channel 0 Base & Current Count Channel 1 Base & Current Address Channel 1 Base & Current Count Channel 2 Base & Current Address Channel 2 Base & Current Count Channel 3 Base & Current Address Channel 3 Base & Current Count Status / Command Write Request Write Single Mask Write Mode Clear Byte Pointer FF Master Clear Clear Mask Read / Write Mask Default Acc RW RW RW RW RW RW RW RW RW WO WO WO WO WO WO RW
Port 87 83 81 82 8F 8B 89 8A Port 92
DMA Page Registers DMA Page - DMA Channel 0 DMA Page - DMA Channel 1 DMA Page - DMA Channel 2 DMA Page - DMA Channel 3 DMA Page - DMA Channel 4 DMA Page - DMA Channel 5 DMA Page - DMA Channel 6 DMA Page - DMA Channel 7 System Control Registers System Control
Port Slave Interrupt Controller Regs Default Acc A0 Slave Interrupt Control -- * A1 Slave Interrupt Mask -- * A0 Slave Interrupt Control Shadow -- RW A1 Slave Interrupt Mask Shadow -- RW * RW accessible if shadow registers are disabled
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Register Overview
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VT82C596B
PCI Function 0 Registers - PCI-to-ISA Bridge Configuration Space PCI-to-ISA Bridge Header Registers Offset 1-0 3-2 5-4 7-6 8 9 A B C D E F 10-27 28-2B 2F-2C 30-33 34-3B 3C 3D 3E 3F PCI Configuration Space Header Vendor ID Device ID Command Status Revision ID Programming Interface Sub Class Code Base Class Code -reserved- (cache line size) -reserved- (latency timer) Header Type Built In Self Test (BIST) -reserved- (base address registers) -reserved- (unassigned) Subsystem ID Read -reserved- (expan. ROM base addr) -reserved- (unassigned) -reserved- (interrupt line) -reserved- (interrupt pin) -reserved- (min gnt) -reserved- (max lat) Default 1106 0596 0087 0200 nn 00 01 06 00 00 80 00 00 00 00 00 00 00 00 00 00 Acc RO RO RW WC RO RO RO RO -- -- RO RO -- -- RO -- -- -- -- -- -- Configuration Space PCI-to-ISA Bridge-Specific Registers Offset Plug and Play Control Default Acc 50 -reserved- (do not program) 24 RW 51-53 -reserved00 -- 54 PCI IRQ Edge / Level Selection 00 RW 55 PnP Routing for External MIRQ0-1 00 RW 56 PnP Routing for PCI INTB-A 00 RW 57 PnP Routing for PCI INTD-C 00 RW 58 PnP Routing for External MIRQ2 00 RW 59 PIRQ Pin Configuration 04 RW 5A KBC / RTC Control x4 RW 5B Internal RTC Test Mode 00 RW 5C DMA Control 00 RW 5F-5D -reserved00 -- Bit 7-4 power-up default value depends on external strapping Offset 61-60 63-62 65-64 67-66 69-68 6B-6A 6D-6C 6F-6E Offset 70 71-73 77-74 7B-78 7F-7C 80 81 82 83 84 85-86 87 88 89 8A-FF Distributed DMA Channel 0 Base Address / Enable Channel 1 Base Address / Enable Channel 2 Base Address / Enable Channel 3 Base Address / Enable Serial IRQ Control Channel 5 Base Address / Enable Channel 6 Base Address / Enable Channel 7 Base Address / Enable Miscellaneous Subsystem ID Write -reservedGPIO / Chip Select Control Programmable Chip Select Control PC/PCI Control Programmable Chip Select Mask ISA Positive Decoding Control 1 ISA Positive Decoding Control 2 ISA Positive Decoding Control 3 ISA Positive Decoding Control 4 -reservedTest 1 Test 2 PLL Control -reservedDefault 0000 0000 0000 0000 0000 0000 0000 0000 Default 00 00 0000 0000 0000 0000 0000 0000 00 00 00 00 00 00 00 00 00 00 Acc RW RW RW RW RW RW RW RW Acc WO -- RW RW RW RW RW RW RW RW -- RW RW RW --
Configuration Space PCI-to-ISA Bridge-Specific Registers Offset 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4F-4E ISA Bus Control ISA Bus Control ISA Test Mode ISA Clock Control ROM Decode Control Keyboard Controller Control Type F DMA Control Miscellaneous Control 1 Miscellaneous Control 2 Miscellaneous Control 3 -reservedIDE Interrupt Routing -reservedDMA / Master Mem Access Control 1 DMA / Master Mem Access Control 2 DMA / Master Mem Access Control 3 Default 00 00 00 00 00 00 00 00 01 00 04 00 00 00 0300 Acc RW RW RW RW RW RW RW RW RW -- RW -- RW RW RW
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Register Overview
7HFKQRORJLHV ,QF
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VT82C596B
PCI Function 1 Registers - IDE Controller Configuration Space IDE Header Registers Offset 1-0 3-2 5-4 7-6 8 9 A B C D E F 13-10 17-14 1B-18 1F-1C 23-20 24-2F 30-33 34-3B 3C 3D 3E 3F PCI Configuration Space Header Default Acc Vendor ID 1106 RO Device ID 0571 RO Command 0080 RO Status 0280 RW Revision ID nn RO Programming Interface 85 RW Sub Class Code 01 RO Base Class Code 01 RO -reserved- (cache line size) 00 -- Latency Timer 00 RW Header Type 00 RO Built In Self Test (BIST) 00 RO Base Address - Pri Data / Command 000001F0 RO Base Address - Pri Control / Status 000003F4 RO Base Address - Sec Data / Command 00000170 RO Base Address - Sec Control / Status 00000374 RO Base Address - Bus Master Control 0000CC01 RW -reserved- (unassigned) 00 -- -reserved- (expan ROM base addr) 00 -- -reserved- (unassigned) 00 -- Interrupt Line 0E RW Interrupt Pin 00 RO Minimum Grant 00 RO Maximum Latency 00 RO Configuration Space IDE-Specific Registers Offset 40 41 42 43 44 45 46 4B-48 4C 4D 4E 4F 53-50 54 55-5F 61-60 62-67 69-68 69-6F 70 71 72-73 74 75 76-77 78 79 7A-7B 7C 7D 7E-7F 83-80 84-87 8B-88 8C-FF Configuration Space IDE Registers Chip Enable IDE Configuration -reserved- (do not program) FIFO Configuration Miscellaneous Control 1 Miscellaneous Control 2 Miscellaneous Control 3 Drive Timing Control Address Setup Time -reserved- (do not program) Sec Non-1F0 Port Access Timing Pri Non-1F0 Port Access Timing UltraDMA33 Extd Timing Control UltraDMA FIFO Control -reservedIDE Primary Sector Size -reservedIDE Secondary Sector Size -reservedIDE Primary Status IDE Primary Interrupt Control -reservedIDE Primary Command 1 IDE Primary Command 2 -reservedIDE Secondary Status IDE Secondary Interrupt Control -reservedIDE Secondary Command 1 IDE Secondary Command 2 -reservedIDE Primary S/G Descriptor Address -reservedIDE Secondary S/G Descriptor Addr -reservedDefault 08 02 09 3A 68 00 C0
A8A8A8A8
FF 00 FF FF 03030303 06 00 0200 00 0200 00 00 00 00 00 00 00 00 00 00 00 00 00 0000 0000 00 0000 0000 00
Acc RW RW RW RW RW RW RW RW RW RW RW RW RW RW -- RW -- RW -- RW RW -- RW RW -- RW RW -- RW RW -- RW -- RW --
I/O Registers - IDE Controller (SFF 8038 v1.0 Compliant Offset IDE I/O Registers Default Acc 0 Primary Channel Command 00 RW 1 -reserved00 -- 2 Primary Channel Status 00 WC 3 -reserved00 -- 4-7 Primary Channel PRD Table Addr 00 RW 8 Secondary Channel Command 00 RW 9 -reserved00 -- A Secondary Channel Status 00 WC B -reserved00 -- C-F Secondary Channel PRD Table Addr 00 RW
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Register Overview
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VT82C596B
PCI Function 2 Registers - USB Controller Configuration Space USB Header Registers Offset 1-0 3-2 5-4 7-6 8 9 A B C D E F 10-1F 23-20 24-3B 3C 3D 3E-3F PCI Configuration Space Header Vendor ID Device ID Command Status Revision ID Programming Interface Sub Class Code Base Class Code Cache Line Size Latency Timer Header Type BIST -reservedBase Address -reservedInterrupt Line Interrupt Pin -reservedDefault 1106 3038 0000 0200 nn 00 03 0C 00 16 00 00 00 00000301 00 00 04 00 Acc RO RO RW WC RO RO RO RO RO RW RO RO -- RW -- RW RO -- I/O Registers - USB Controller Offset 1-0 3-2 5-4 7-6 B-8 C 11-10 13-12 USB I/O Registers USB Command USB Status USB Interrupt Enable Frame Number Frame List Base Address Start Of Frame Modify Port 1 Status / Control Port 2 Status / Control Default 0000 0000 0000 0000 00000000 40 0080 0080 Acc RW WC RW RW RW RW WC WC
Configuration Space USB-Specific Registers Offset 40 41 42-43 44-45 46-47 48-5F 60 61-BF C1-C0 C2-FF USB Control Miscellaneous Control 1 Miscellaneous Control 2 -reserved-reserved- (test only, do not program) -reserved- (test) -reservedSerial Bus Release Number -reservedLegacy Support -reservedDefault 00 00 00 Acc RW RW RO RW RO -- RO -- RW --
00 10 00 2000 00
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VT82C596B
PCI Function 3 Registers - Power Management Configuration Space Power Management Header Registers Offset PCI Configuration Space Header Default Acc 1-0 Vendor ID 1106 RO 3-2 Device ID 3050 RO 5-4 Command 0000 RO 7-6 Status 0280 WC 8 Revision ID nn RO 9 Programming Interface RO 00 A Sub Class Code RO 00 B Base Class Code RO 00 C Cache Line Size 00 RO D Latency Timer 00 RO E Header Type 00 RO F BIST 00 RO 10-3F -reserved00 -- Default values may be changed by writing to offsets 61-63h. Configuration Space Power Management-Specific Registers Offset 40 41 42 43 45-44 47-46 4B-48 4C 4D 4E-4F 53-50 54 55 56-57 5B-58 5C-60 61 62 63 64-8F Offset 93-90 94-D1 D2 D3 D4 D5 D6 D7-FF Power Management Debounce Control General Configuration SCI Interrupt Configuration -reservedPrimary Interrupt Channel Secondary Interrupt Channel Power Mgmt I/O Base (256 Bytes) Host Bus Power Management Control Clock Stop Control -reservedGP0/1 Timer Control GPIO Select Wakeup Control -reservedGP2/3 Timer Control -reservedWrite value for Offset 9 (Prog Intfc) Write value for Offset A (Sub Class) Write value for Offset B (Base Class) -reservedSystem Management Bus SMBus I/O Base -reservedSMBus Control SMBus Host Slave Command SMBus Slave Address for Port 1 SMBus Slave Address for Port 2 SMBus Revision ID -reservedDefault 00 00 00 00 0000 0000 0000 0001 00 00 00 0000 0000 00 00 00 0000 0000 00 00 00 00 00 Default 0000 0001 00 00 00 00 00 nn 00 Acc RW RW RW -- RW RW RW RW RW -- RW RW RW -- RW -- WO WO WO -- Acc RW -- RW RW RW RW RO --
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Register Overview
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VT82C596B
I/O Space Power Management- Registers Default 00 00 00 00 00 00 00 00 00 00 0000 0000 00 Acc WC RW RW RW RW RW RW RW RW RO RW RO -- Offset 1-0 3-2 5-4 6-7 B-8 C-F Offset 13-10 14 15 16-1F Offset 21-20 23-22 25-24 26-27 Offset 29-28 2B-2A 2D-2C 2E 2F 33-30 37-34 3B-38 3C-3F Offset 40 41-43 45-44 46-47 4B-48 4F-4C 50-FF Basic Control / Status Registers Power Management Status Power Management Enable Power Management Control -reservedPower Management Timer -reservedProcessor Registers Processor and PCI Bus Control Processor LVL2 Processor LVL3 -reservedGeneral Purpose Registers General Purpose Status General Purpose SCI Enable General Purpose SMI Enable -reservedGeneric Registers Global Status Global Enable Global Control -reservedSMI Command Primary Activity Detect Status Primary Activity Detect Enable GP Timer Reload Enable -reservedGeneral Purpose I/O Registers General Purpose Control -reservedExternal SMI Input Value -reservedGPI Port Input Value GPO Port Output Value -reservedDefault 0000 0000 0000 00 0000 0000 00 Default 0000 0000 00 00 00 Default 0000 0000 0000 00 Default 0000 0000 0010 00 00 0000 0000 0000 0000 0000 0000 00 Default 00 00 input 00 input 7FFFFFFF 00 Acc WC RW RW -- RW -- Acc RW RO RO -- Acc WC RW RW -- Acc WC RW RW -- RW WC RW RW -- Acc RW -- RO -- RO RW --
I/O Space System Management Bus Registers Offset 0 1 2 3 4 5 6 7 8 9 A-B C-D E-F System Management Bus SMBus Host Status SMBus Slave Status SMBus Host Control SMBus Host Command SMBus Host Address SMBus Host Data 0 SMBus Host Data 1 SMBus Block Data SMBus Slave Control SMBus Shadow Command SMBus Slave Event SMBus Slave Data -reserved-
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Register Overview
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Configuration Space I/O
Mechanism #1 These ports respond only to double-word accesses. Byte or word accesses will be passed on unchanged. Port CFB-CF8 - Configuration Address ......................... RW 31 Configuration Space Enable 0 Disabled .................................................default 1 Convert configuration data port writes to configuration cycles on the PCI bus ........................................ always reads 0 30-24 Reserved 23-16 PCI Bus Number Used to choose a specific PCI bus in the system 15-11 Device Number Used to choose a specific device in the system 10-8 Function Number Used to choose a specific function if the selected device supports multiple functions 7-2 Register Number Used to select a specific DWORD in the device's configuration space ........................................ always reads 0 1-0 Fixed Port CFF-CFC - Configuration Data .............................. RW
Refer to PCI Bus Specification Version 2.1 for further details on operation of the above configuration registers.
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Configuration Space I/O
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Port 92h - System Control ................................................ RW 7-6 Hard Disk Activity LED Status 0 Off .................................................... default 1-3 On ........................................always reads 0 5-4 Reserved 3 Power-On Password Bytes Inaccessable ..default=0 ........................................always reads 0 2 Reserved 1 A20 Address Line Enable 0 A20 disabled / forced 0 (real mode) ...... default 1 A20 address line enabled 0 High Speed Reset 0 Normal 1 Briefly pulse system reset to switch from protected mode to real mode
Register Descriptions
Legacy I/O Ports This group of registers includes the DMA Controllers, Interrupt Controllers, and Timer/Counters as well as a number of miscellaneous ports originally implemented using discrete logic on original PC/AT motherboards. All of the registers listed are integrated on-chip. These registers are implemented in a precise manner for backwards compatibility with previous generations of PC hardware. These registers are listed for information purposes only. Detailed descriptions of the actions and programming of these registers are included in numerous industry publications (duplication of that information here is beyond the scope of this document). All of these registers reside in I/O space. Port 61 - Misc Functions & Speaker Control ................. RW ........................................ always reads 0 7 Reserved 6 IOCHCK# Active................................................. RO This bit is set when the ISA bus IOCHCK# signal is asserted. Once set, this bit may be cleared by setting bit-3 of this register. Bit-3 should be cleared to enable recording of the next IOCHCK#. IOCHCK# generates NMI to the CPU if NMI is enabled. 5 Timer/Counter 2 Output ..................................... RO This bit reflects the output of Timer/Counter 2 without any synchronization. 4 Refresh Detected .................................................. RO This bit toggles on every rising edge of the ISA bus REFRESH# signal. 3 IOCHCK# Disable .............................................. RW 0 Enable IOCHCK# assertions..................default 1 Force IOCHCK# inactive and clear any "IOCHCK# Active" condition in bit-6 ........................................ RW, default=0 2 Reserved 1 Speaker Enable.................................................... RW 0 Disable ...................................................default 1 Enable Timer/Ctr 2 output to drive SPKR pin 0 Timer/Counter 2 Enable..................................... RW 0 Disable ...................................................default 1 Enable Timer/Counter 2
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Register Descriptions - Legacy I/O Ports
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Port 64 - Keyboard / Mouse Status .................................. RO 0 Keyboard Output Buffer Full 0 Keyboard Output Buffer Empty............. default 1 Keyboard Output Buffer Full 1 Input Buffer Full 0 Input Buffer Empty................................ default 1 Input Buffer Full 2 System Flag 0 Power-On Default .................................. default 1 Self Test Successful 3 Command / Data 0 Last write was data write ....................... default 1 Last write was command write 4 Keylock Status 0 Locked 1 Free 5 Mouse Output Buffer Full 0 Mouse output buffer empty.................... default 1 Mouse output buffer holds mouse data 6 General Receive / Transmit Timeout 0 No error ................................................. default 1 Error 7 Parity Error 0 No parity error (odd parity received)..... default 1 Even parity occurred on last byte received from keyboard / mouse KBC Control Register .......... (R/W via Commands 20h/60h) ........................................always reads 0 7 Reserved 6 PC Compatibility 0 Disable scan conversion 1 Convert scan codes to PC format; convert 2byte break sequences to 1-byte PC-compatible break codes ............................................ default 5 Mouse Disable 0 Enable Mouse Interface ......................... default 1 Disable Mouse Interface 4 Keyboard Disable 0 Enable Keyboard Interface .................... default 1 Disable Keyboard Interface 3 Keyboard Lock Disable 0 Enable Keyboard Inhibit Function......... default 1 Disable Keyboard Inhibit Function 2 System Flag ................................................default=0 This bit may be read back as status register bit-2 1 Mouse Interrupt Enable 0 Disable mouse interrupts ....................... default 1 Generate interrupt on IRQ12 when mouse data comes in output bufer 0 Keyboard Interrupt Enable 0 Disable Keyboard Interrupts.................. default 1 Generate interrupt on IRQ1 when output buffer has been written.
Keyboard Controller Registers The keyboard controller handles the keyboard and mouse interfaces. Two ports are used: port 60 and port 64. Reads from port 64 return a status byte. Writes to port 64h are command codes (see command code list following the register descriptions). Input and output data is transferred via port 60. A "Control" register is also available. It is accessable by writing commands 20h / 60h to the command port (port 64h); The control byte is written by first sending 60h to the command port, then sending the control byte value. The control register may be read by sending a command of 20h to port 64h, waiting for "Output Buffer Full" status = 1, then reading the control byte value from port 60h. Traditional (non-integrated) keyboard controllers have an "Input Port" and an "Output Port" with specific pins dedicated to certain functions and other pins available for general purpose I/O. Specific commands are provided to set these pins high and low. All outputs are "open-collector" so to allow input on one of these pins, the output value for that pin would be set high (non-driving) and the desired input value read on the input port. These ports are defined as follows: Lo Code Hi Code Bit Input Port 0 P10 - Keyboard Data In B0 B8 1 P11 - Mouse Data In B1 B9 2 P12 - Turbo Pin (PS/2 mode only) B2 BA 3 P13 - user-defined B3 BB 4 P14 - user-defined B6 BE 5 P15 - user-defined B7 BF 6 P16 - user-defined - - 7 P17 - undefined - - Lo Code Hi Code Bit Output Port 0 P20 - SYSRST (1=execute reset) - - 1 P21 - GATEA20 (1=A20 enabled) - - 2 P22 - Mouse Data Out B4 BC 3 P23 - Mouse Clock Out B5 BD 4 P24 - Keyboard OBF Interrupt (IRQ1) - - 5 P25 - Mouse OBF Interrupt (IRQ 12) - - 6 P26 - Keyboard Clock Out - - 7 P27 - Keyboard Data Out - - Bit Test Port Lo Code Hi Code 0 T0 - Keyboard Clock In - - 1 T1 - Mouse Clock In - - Note: Command code C0h transfers input port data to the output buffer. Command code D0h copies output port values to the output buffer. Command code E0h transfers test input port data to the output buffer. Port 60 - Keyboard Controller Input Buffer ................. WO Only write to port 60h if port 64h bit-1 = 0 (1=full). Port 60 - Keyboard Controller Output Buffer ................RO Only read from port 60h if port 64h bit-0 = 1 (0=empty).
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Register Descriptions - Legacy I/O Ports
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Port 64 - Keyboard / Mouse Command .......................... WO This port is used to send commands to the keyboard / mouse controller. The command codes recognized by the VT82C596B are listed n the table below. Note: The VT82C596B Keyboard Controller is compatible with the VIA VT82C42 Industry-Standard Keyboard Controller except that due to its integrated nature, many of the input and output port pins are not available externally for use as general purpose I/O pins (even though P13-P16 are set on power-up as strapping options). In other words, many of the commands below are provided and "work", but otherwise perform no useful function (e.g., commands that set P12-P17 high or low). Also note that setting P10-11, P22-23, P26-27, and T0-1 high or low directly serves no useful purpose, since these bits are used to implement the keyboard and mouse ports and are directly controlled by keyboard controller logic.
Table 4. Keyboard Controller Command Codes
Code 20h 21-3Fh 60h 61-7Fh 9xh A1h A4h A7h A8h A9h Keyboard Command Code Description Read Control Byte (next byte is Control Byte) Read SRAM Data (next byte is Data Byte) Write Control Byte (next byte is Control Byte) Write SRAM Data (next byte is Data Byte) Write low nibble (bits 0-3) to P10-P13 Output Keyboard Controller Version # Test if Password is installed (always returns F1h to indicate not installed) Disable Mouse Interface Enable Mouse Interface Mouse Interface Test (puts test results in port 60h) (value: 0=OK, 1=clk stuck low, 2=clk stuck high, 3=data stuck lo, 4=data stuck hi, FF=general error) KBC self test (returns 55h if OK, FCh if not) Keyboard Interface Test (see A9h Mouse Test) Disable Keyboard Interface Enable Keyboard Interface Return Version # Set P10 low Set P11 low Set P12 low Set P13 low Set P22 low Set P23 low Set P14 low Set P15 low Set P10 high Set P11 high Set P12 high Set P13 high Set P22 high Set P23 high Set P14 high Set P15 high Code C0h C1h C2h C8h C9h CAh D0h D1h D2h D3h Keyboard Command Code Description Read input port (read P10-17 input data to the output buffer) Poll input port low (read input data on P11-13 repeatably & put in bits 5-7 of status Poll input port high (same except P15-17) Unblock P22-23 (use before D1 to change active mode) Reblock P22-23 (protection mechanism for D1) Read mode (output KBC mode info to port 60 output buffer (bit-0=0 if ISA, 1 if PS/2) Read Output Port (copy P10-17 output port values to port 60) Write Output Port (data byte following is written to keyboard output port as if it came from keyboard) Write Keyboard Output Buffer & clear status bit-5 (write following byte to keyboard) Write Mouse Output Buffer & set status bit-5 (write following byte to mouse; put value in mouse input buffer so it appears to have come from the mouse) Write Mouse (write following byte to mouse) Read test inputs (T0-1 read to bits 0-1 of resp byte) Set P23-P21 per command bits 3-1 Pulse P23-P20 low for 6usec per command bits 3-0
AAh ABh ADh AEh AFh B0h B1h B2h B3h B4h B5h B6h B7h B8h B9h BAh BBh BCh BDh BEh BFh
D4h E0h Exh Fxh
All other codes not listed are undefined.
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Register Descriptions - Legacy I/O Ports
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Ports C0-DF - Slave DMA Controller Channels 0-3 of the Slave DMA Controller control System DMA Channels 4-7. There are 16 Slave DMA Controller registers: I/O Address Bits 15-0 0000 0000 1100 000x 0000 0000 1100 001x 0000 0000 1100 010x 0000 0000 1100 011x 0000 0000 1100 100x 0000 0000 1100 101x 0000 0000 1100 110x 0000 0000 1100 111x 0000 0000 1101 000x 0000 0000 1101 001x 0000 0000 1101 010x 0000 0000 1101 011x 0000 0000 1101 100x 0000 0000 1101 101x 0000 0000 1101 110x 0000 0000 1101 111x Register Name Ch 0 Base / Current Address Ch 0 Base / Current Count Ch 1 Base / Current Address Ch 1 Base / Current Count Ch 2 Base / Current Address Ch 2 Base / Current Count Ch 3 Base / Current Address Ch 3 Base / Current Count Status / Command Write Request Write Single Mask Write Mode Clear Byte Pointer F/F Master Clear Clear Mask Read/Write All Mask Bits
DMA Controller I/O Registers Ports 00-0F - Master DMA Controller Channels 0-3 of the Master DMA Controller control System DMA Channels 0-3. There are 16 Master DMA Controller registers: I/O Address Bits 15-0 0000 0000 000x 0000 0000 0000 000x 0001 0000 0000 000x 0010 0000 0000 000x 0011 0000 0000 000x 0100 0000 0000 000x 0101 0000 0000 000x 0110 0000 0000 000x 0111 0000 0000 000x 1000 0000 0000 000x 1001 0000 0000 000x 1010 0000 0000 000x 1011 0000 0000 000x 1100 0000 0000 000x 1101 0000 0000 000x 1110 0000 0000 000x 1111 Register Name Ch 0 Base / Current Address Ch 0 Base / Current Count Ch 1 Base / Current Address Ch 1 Base / Current Count Ch 2 Base / Current Address Ch 2 Base / Current Count Ch 3 Base / Current Address Ch 3 Base / Current Count Status / Command Write Request Write Single Mask Write Mode Clear Byte Pointer F/F Master Clear Clear Mask R/W All Mask Bits RW RW RW RW RW RW RW RW RW WO WO WO WO WO WO RW
RW RW RW RW RW RW RW RW RW WO WO WO WO WO WO WO
Note that not all bits of the address are decoded. Note that not all bits of the address are decoded. The Master DMA Controller is compatible with the Intel 8237 DMA Controller chip. Detailed descriptions of 8237 DMA Controller operation can be obtained from the Intel Peripheral Components Data Book and numerous other industry publications. The Slave DMA Controller is compatible with the Intel 8237 DMA Controller chip. Detailed description of 8237 DMA controller operation can be obtained from the Intel Peripheral Components Data Book and numerous other industry publications.
Ports 80-8F - DMA Page Registers There are eight DMA Page Registers, one for each DMA channel. These registers provide bits 16-23 of the 24-bit address for each DMA channel (bits 0-15 are stored in registers in the Master and Slave DMA Controllers). They are located at the following I/O Port addresses: I/O Address Bits 15-0 0000 0000 1000 0111 0000 0000 1000 0011 0000 0000 1000 0001 0000 0000 1000 0010 0000 0000 1000 1111 0000 0000 1000 1011 0000 0000 1000 1001 0000 0000 1000 1010 Register Name Channel 0 DMA Page (M-0).........RW Channel 1 DMA Page (M-1).........RW Channel 2 DMA Page (M-2).........RW Channel 3 DMA Page (M-3).........RW Channel 4 DMA Page (S-0) ..........RW Channel 5 DMA Page (S-1) ..........RW Channel 6 DMA Page (S-2) ..........RW Channel 7 DMA Page (S-3) .........RW
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Interrupt Controller Shadow Registers The following shadow registers are enabled by setting bit 4 of Rx47 to 1 (offset 47h in the PCI-ISA Bridge function 0 register group). If the shadow registers are enabled, they are read back at the indicated I/O port instead of the standard interrupt controller registers (writes to the interrupt controller register ports are directed to the standard interrupt controller registers). Port 20 - Master Interrupt Control Shadow ................... RO ........................................always reads 0 7-5 Reserved 4 OCW3 bit 5 3 OCW2 bit 7 2 ICW4 bit 4 1 ICW4 bit 1 0 ICW1 bit 3 Port 21 - Master Interrupt Mask Shadow ....................... RO ........................................always reads 0 7-5 Reserved 4-0 T7-T3 of Interrupt Vector Address Port A0 - Slave Interrupt Control Shadow ..................... RO ........................................always reads 0 7-5 Reserved 4 OCW3 bit 5 3 OCW2 bit 7 2 ICW4 bit 4 1 ICW4 bit 1 0 ICW1 bit 3 Port A1 - Slave Interrupt Mask Shadow ........................ RO ........................................always reads 0 7-5 Reserved 4-0 T7-T3 of Interrupt Vector Address Timer / Counter Registers Ports 40-43 - Timer / Counter Registers There are 4 Timer / Counter registers: I/O Address Bits 15-0 0000 0000 010x xx00 0000 0000 010x xx01 0000 0000 010x xx10 0000 0000 010x xx11 Register Name Timer / Counter 0 Count Timer / Counter 1 Count Timer / Counter 2 Count Timer / Counter Cmd Mode RW RW RW WO
Interrupt Controller Registers Ports 20-21 - Master Interrupt Controller The Master Interrupt Controller controls system interrupt channels 0-7. Two registers control the Master Interrupt Controller. They are: I/O Address Bits 15-0 0000 0000 001x xxx0 0000 0000 001x xxx1 Register Name Master Interrupt Control Master Interrupt Mask RW RW
Note that not all bits of the address are decoded. The Master Interrupt Controller is compatible with the Intel 8259 Interrupt Controller chip. Detailed descriptions of 8259 Interrupt Controller operation can be obtained from the Intel Peripheral Components Data Book and numerous other industry publications.
Ports A0-A1 - Slave Interrupt Controller The Slave Interrupt Controller controls system interrupt channels 8-15. The slave system interrupt controller also occupies two register locations: I/O Address Bits 15-0 0000 0000 101x xxx0 0000 0000 101x xxx1 Register Name Slave Interrupt Control Slave Interrupt Mask RW RW
Note that not all address bits are decoded. The Slave Interrupt Controller is compatible with the Intel 8259 Interrupt Controller chip. Detailed descriptions of 8259 Interrupt Controller operation can be obtained from the Intel Peripheral Components Data Book and numerous other industry publications.
Note that not all bits of the address are decoded. The Timer / Counters are compatible with the Intel 8254 Timer / Counter chip. Detailed descriptions of 8254 Timer / Counter operation can be obtained from the Intel Peripheral Components Data Book and numerous other industry publications.
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Register Descriptions - Legacy I/O Ports
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Offset 00 01 02 03 04 Binary Range BCD Range Description 00-3Bh 00-59h Seconds 00-3Bh 00-59h Seconds Alarm 00-3Bh 00-59h Minutes 00-3Bh 00-59h Minutes Alarm am 12hr: 01-1Ch 01-12h Hours pm 12hr: 81-8Ch 81-92h 24hr: 00-17h 00-23h 01-12h Hours Alarm am 12hr: 01-1Ch pm 12hr: 81-8Ch 81-92h 24hr: 00-17h 00-23h 01-07h Day of the Week Sun=1: 01-07h 01-1Fh 01-31h Day of the Month 01-0Ch 01-12h Month 00-63h 00-99h Year Register A 7 UIP Update In Progress 6-4 DV2-0 Divide (010=ena osc & keep time) 3-0 RS3-0 Rate Select for Periodic Interrupt Register B 7 SET 6 PIE 5 AIE 4 UIE 3 SQWE 2 DM 1 24/12 0 DSE Register C 7 IRQF 6 PF 5 AF 4 UF 3-0 0 Register D 7 VRT 6-0 0
CMOS / RTC Registers Port 70 - CMOS Address ................................................. WO 7 NMI Disable.........................................................WO 0 Enable NMI Generation. NMI is asserted on encountering IOCHCK# on the ISA bus or SERR# on the PCI bus. 1 Disable NMI Generation ........................default 6-0 CMOS Address (lower 128 bytes).......................WO Port 71 - CMOS Data........................................................ RW 7-0 CMOS Data (128 bytes) Note: Ports 70-71 may be accessed if Rx5A bit-2 is set to one to select the internal RTC. If Rx5A bit-2 is set to zero, accesses to ports 70-71 will be directed to an external RTC. 06 07 08 09 0A
05
Port 72 - CMOS Address .................................................. RW 7-0 CMOS Address (256 bytes)................................. RW Port 73 - CMOS Data........................................................ RW 7-0 CMOS Data (256 bytes) Note: Ports 72-73 may be accessed if Rx5A bit-2 is set to one to select the internal RTC. If Rx5A bit-2 is set to zero, accesses to ports 72-73 will be directed to an external RTC.
0B
Port 74 - CMOS Address .................................................. RW 7-0 CMOS Address (256 bytes)................................. RW Port 75 - CMOS Data........................................................ RW 7-0 CMOS Data (256 bytes) Note: Ports 74-75 may be accessed only if Function 0 Rx5B bit-1 is set to one to enable the internal RTC SRAM and if Rx48 bit-3 (Port 74/75 Access Enable) is set to one to enable port 74/75 access. Ports 70-71 are compatible with PC industrystandards and may be used to access the lower 128 bytes of the 256-byte on-chip CMOS RAM. Ports 72-73 may be used to access the full extended 256byte space. Ports 74-75 may be used to access the full on-chip extended 256-byte space in cases where the on-chip RTC is disabled. The system Real Time Clock (RTC) is part of the "CMOS" block. The RTC control registers are located at specific offsets in the CMOS data area (00Dh and 7D-7Fh). Detailed descriptions of CMOS / RTC operation and programming can be obtained from the VIA VT82887 Data Book or numerous other industry publications. For reference, the definition of the RTC register locations and bits are summarized in the following table: 0D
Inhibit Update Transfers Periodic Interrupt Enable Alarm Interrupt Enable Update Ended Interrupt Enable No function (read/write bit) Data Mode (0=BCD, 1=binary) Hours Byte Format (0=12, 1=24) Daylight Savings Enable
0C
Note:
Interrupt Request Flag Periodic Interrupt Flag Alarm Interrupt Flag Update Ended Flag Unused (always read 0)
Reads 1 if VBAT voltage is OK Unused (always read 0)
0E-7C Software-Defined Storage Registers (111 Bytes) Offset 7D 7E 7F Extended Functions Date Alarm Month Alarm Century Field Binary Range BCD Range 01-1Fh 01-31h 01-0Ch 01-12h 13-14h 19-20h
Note:
80-FF Software-Defined Storage Registers (128 Bytes) (See also Function 0 Rx5B[3] and Rx77[2-1])
Table 5. CMOS Register Summary
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Function 0 Registers - PCI to ISA Bridge All registers are located in the function 0 PCI configuration space of the VT82C596B. These registers are accessed through PCI configuration mechanism #1 via I/O address CF8/CFC. PCI Configuration Space Header Offset 1-0 - Vendor ID = 1106h .........................................RO Offset 3-2 - Device ID = 0596h ..........................................RO Offset 5-4 - Command ....................................................... RW ........................................ always reads 0 15-8 Reserved 7 Address / Data Stepping 0 Disable 1 Enable ....................................................default ........................................ always reads 0 6-4 Reserved 3 Special Cycle Enable .....Normally RW, default = 0 2 Bus Master ........................................ always reads 1 1 Memory Space.................. Normally RO, reads as 1 0 I/O Space ...................... Normally RO, reads as 1 If the test bit at offset 46 bit-4 is set, access to the above indicated bits is reversed: bit-3 above becomes read only (reading back 1) and bits 0-1 above become read / write (with a default of 1). Offset 7-6 - Status ........................................................... RWC 15 Detected Parity Error .................... write one to clear 14 Signalled System Error...................... always reads 0 13 Signalled Master Abort ................. write one to clear 12 Received Target Abort .................. write one to clear 11 Signalled Target Abort .................. write one to clear 10-9 DEVSEL# Timing .................... fixed at 01 (medium) 8 Data Parity Detected.......................... always reads 0 7 Fast Back-to-Back Capable............... always reads 0 ........................................ always reads 0 6-0 Reserved Offset 8 - Revision ID = nn ................................................ RO 7-0 Revision ID (00h is first silicon) Offset 9 - Program Interface = 00h .................................. RO Offset A - Sub Class Code = 01h....................................... RO Offset B - Class Code = 06h .............................................. RO Offset E - Header Type = 80h ........................................... RO 7-0 Header Type Code......... 80h (Multifunction Device) Offset F - BIST = 00h ........................................................ RO Offset 2F-2C - Subsystem ID ............................................ RO Use offset 70-73 to change the value returned.
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PCI Function 0 Registers - PCI-to-ISA Bridge
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ISA Bus Control Offset 40 - ISA Bus Control.............................................. RW 7 ISA Command Delay 0 Normal ...................................................default 1 Extra 6 Extended ISA Bus Ready 0 Disable ...................................................default 1 Enable 5 ISA Slave Wait States 0 4 Wait States ..........................................default 1 5 Wait States 4 Chipset I/O Wait States 0 2 Wait States ..........................................default 1 4 Wait States 3 I/O Recovery Time 0 Disable ...................................................default 1 Enable 2 Extend-ALE 0 Disable ...................................................default 1 Enable 1 ROM Wait States 0 1 Wait State............................................default 1 0 Wait States 0 ROM Write 0 Disable ...................................................default 1 Enable Offset 41 - ISA Test Mode ................................................ RW 7 Bus Refresh Arbitration (do not program) default=0 6 XRDY Test Mode (do not program)........... default=0 5 Port 92 Fast Reset 0 Disable ...................................................default 1 Enable 4 A20G Emulation (do not program)............. default=0 3 Double DMA Clock 0 Disable (DMA Clock = 1/2 ISA Clock) ...default 1 Enable (DMA Clock = ISA Clock) 2 SHOLD Lock During INTA (do not program) def=0 1 Refresh Request Test Mode (do not program) def=0 0 ISA Refresh 0 Disable ...................................................default 1 Enable Offset 42 - ISA Clock Control.......................................... RW 7 Latch IO16# 0 Enable (recommended setting) .............. default 1 Disable 6 MS16# Output 0 Enable (recommended setting) .............. default 1 Disable 5 Master Request Test Mode (do not program)..def=0 4 Reserved (no defined function) .................default = 0 3 ISA CLOCK Select Enable 0 ISA Clock = PCICLK/4......................... default 1 ISA Clock selected per bits 2-0 2-0 ISA Bus Clock Select (if bit-3 = 1) 000 PCICLK/3.............................................. default 001 PCICLK/2 010 PCICLK/4 011 PCICLK/6 100 PCICLK/5 101 PCICLK/10 110 PCICLK/12 111 OSC Note: Procedure for ISA CLOCK switching: 1) Set bit 3 to 0; 2) Change value of bit 2-0; 3) Set bit 3 to 1
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PCI Function 0 Registers - PCI-to-ISA Bridge
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Offset 46 - Miscellaneous Control 1 ................................ RW 7 PCI Master Write Wait States 0 0 Wait States.......................................... default 1 1 Wait State 6 Gate INTRQ 0 Disable................................................... default 1 Enable 5 Flush Line Buffer for Int or DMA IOR Cycle 0 Disable................................................... default 1 Enable 4 Config Command Reg Rx04 Access (Test Only) 0 Normal: Bits 0-1=RO, Bit 3=RW ......... default 1 Test Mode: Bits 0-1=RW, Bit-3=RO 3 Reserved (do not program) ........................default = 0 2 Reserved (no function) ..............................default = 0 1 PCI Burst Read Interruptability 0 Allow burst reads to be interrupted........ default 1 Don't allow PCI burst reads to be interrupted 0 Post Memory Write Enable 0 Disable................................................... default 1 Enable The Post Memory Write function is automatically enabled when Delay Transaction (see Rx47 bit-6 below) is enabled, independent of the state of this bit. Offset 47 - Miscellaneous Control 2 ................................ RW 7 CPU Reset Source 0 Use CPURST as CPU Reset .................. default 1 Use INIT as CPU Reset 6 PCI Delay Transaction Enable 0 Disable................................................... default 1 Enable The "Post Memory Write" function is automatically enabled when this bit is enabled, independent of the state of Rx46 bit-0 above. 5 EISA 4D0/4D1 Port Enable 0 Disable (ignore ports 4D0-1) ................. default 1 Enable (ports 4D0-1 per EISA specification) 4 Interrupt Controller Shadow Register Enable 0 Disable................................................... default 1 Enable 3 Reserved (always program to 0)..............default = 0 Note: Always mask this bit. This bit may read back as either 0 or 1 but must always be programmed with 0. 2 Write Delay Transaction Time-Out Timer Enable 0 Disable................................................... default 1 Enable 1 Read Delay Transaction Time-Out Timer Enable 0 Disable................................................... default 1 Enable 0 Software PCI Reset ......write 1 to generate PCI reset
Offset 43 - ROM Decode Control .................................... RW Setting these bits enables the indicated address range to be included in the ROMCS# decode: 7 6 5 4 5 4 3 2 1 0 FFFE0000h-FFFEFFFFh .......................... default=0 FFF80000h-FFFDFFFFh ......................... default=0 FFF00000h-FFF7FFFFh (new)................. default=0 000E0000h-000EFFFFh (new) .................. default=0 000E8000h-000EFFFFh (old).................... default=0 000E0000h-000E7FFFh (old) .................... default=0 000D8000h-000DFFFFh ........................... default=0 000D0000h-000D7FFFh ............................ default=0 000C8000h-000CFFFFh ........................... default=0 000C0000h-000C7FFFh............................. default=0
Offset 44 - Keyboard Controller Control ........................ RW 7 KBC Timeout Test (do not program) ....... default = 0 6-4 Reserved (do not program)........................ default = 0 3 Mouse Lock Enable 0 Disabled .................................................default 1 Enabled 2-1 Reserved (do not program)........................ default = 0 0 Reserved (no function) .............................. default = 0 Offset 45 - Type F DMA Control ..................................... RW 7 ISA Master / DMA to PCI Line Buffer.... default=0 6 DMA type F Timing on Channel 7 ........... default=0 5 DMA type F Timing on Channel 6 ........... default=0 4 DMA type F Timing on Channel 5 ........... default=0 3 DMA type F Timing on Channel 3 ........... default=0 2 DMA type F Timing on Channel 2 ........... default=0 1 DMA type F Timing on Channel 1 ........... default=0 0 DMA type F Timing on Channel 0 ........... default=0
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PCI Function 0 Registers - PCI-to-ISA Bridge
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VT82C596B
4C - ISA DMA/Master Memory Access Control 1 ........ RW 7-0 PCI Memory Hole Bottom Address These bits correspond to HA[23:16] ............default=0 4D - ISA DMA/Master Memory Access Control 2 ........ RW 7-0 PCI Memory Hole Top Address (HA[23:16]) These bits correspond to HA[23:16] ............default=0 Note: Access to the memory defined in the PCI memory hole will not be forwarded to PCI. This function is disabled if the top address less than or equal to the bottom address.
Offset 48 - Miscellaneous Control 3 ................................. RW 7 Low Voltage CPU Interface 0 Disable ...................................................default 1 Enable 6-4 Reserved (Do Not Program).............. always reads 0 3 Extra RTC Port 74/75 Enable 0 Disable ...................................................default 1 Enable 2 Integrated USB Controller Disable 0 Enable.....................................................default 1 Disable 1 Integrated IDE Controller Disable 0 Enable.....................................................default 1 Disable 0 512K PCI Memory Decode 0 Use Rx4E[15-12] to select top of PCI memory 1 Use contents of Rx4E[15-12] plus 512K as top of PCI memory .......................................default Offset 4A - IDE Interrupt Routing .................................. RW 7 Wait for PGNT Before Grant to ISA Master / DMA 0 Disable ...................................................default 1 Enable (must be set to 1) 6 Bus Select for Access to I/O Devices Below 100h 0 Access ports 00-FFh via XD bus............default 1 Access ports 00-FFh via SD bus (applies to external devices only; internal devices such as the mouse controller are not effected) 5-4 Reserved (do not program) ..................... default = 0 3-2 IDE Second Channel IRQ Routing 00 IRQ14 01 IRQ15.....................................................default 10 IRQ10 11 IRQ11 1-0 IDE Primary Channel IRQ Routing 00 IRQ14.....................................................default 01 IRQ15 10 IRQ10 11 IRQ11
4F-4E - ISA DMA/Master Memory Access Control 3 ... RW 15-12 Top of PCI Memory for ISA DMA/Master accesses 0000 1M .................................................... default 0001 2M ... ... 1111 16M Note: All ISA DMA / Masters that access addresses higher than the top of PCI memory will not be directed to the PCI bus. 11 Forward E0000-EFFFF Accesses to PCI........def=0 10 Forward A0000-BFFFF Accesses to PCI .......def=0 9 Forward 80000-9FFFF Accesses to PCI ........def=1 8 Forward 00000-7FFFF Accesses to PCI ........def=1 7 Forward DC000-DFFFF Accesses to PCI ......def=0 6 Forward D8000-DBFFF Accesses to PCI ......def=0 5 Forward D4000-D7FFF Accesses to PCI .......def=0 4 Forward D0000-D3FFF Accesses to PCI .......def=0 3 Forward CC000-CFFFF Accesses to PCI .....def=0 2 Forward C8000-CBFFF Accesses to PCI ......def=0 1 Forward C4000-C7FFF Accesses to PCI .......def=0 0 Forward C0000-C3FFF Accesses to PCI .......def=0
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PCI Function 0 Registers - PCI-to-ISA Bridge
7HFKQRORJLHV ,QF
:H &RQQHFW
VT82C596B
Plug and Play Control Offset 50 - Reserved (Do Not Program) .......................... RW .......................................... default = 24h 7-0 Reserved Offset 54 - PCI IRQ Polarity ............................................ RW ........................................ always reads 0 7-4 Reserved 3 PIRQA# 0 Non-invert (Level)..................................default 1 Invert (Edge) 2 PIRQB# 0 Non-invert (Level)..................................default 1 Invert (Edge) 1 PIRQC# 0 Non-invert (Level)..................................default 1 Invert (Edge) 0 PIRQD# 0 Non-invert (Level)..................................default 1 Invert (Edge) Note: PIRQA-D# normally connect to PCI interrupt pins INTA-D# (see pin definitions for more information). Offset 58 - PNP IRQ Routing 4 ....................................... RW ........................................always reads 0 7-4 Reserved 3-0 PIRQ2 Routing (see PnP IRQ routing table) PnP IRQ Routing Table 0000 Disabled................................................. default 0001 IRQ1 0010 Reserved 0011 IRQ3 0100 IRQ4 0101 IRQ5 0110 IRQ6 0111 IRQ7 1000 Reserved 1001 IRQ9 1010 IRQ10 1011 IRQ11 1100 IRQ12 1101 Reserved 1110 IRQ14 1111 IRQ15 Offset 59 - PIRQ Pin Configuration (04h) ...................... RW ........................................always reads 0 7-3 Reserved 2 PIRQ2 / GPI21 Selection (Pin G3) 0 PIRQ2 1 GPI21 .................................................... default 1 PIRQ1 / KEYLOCK Selection (Pin J4) 0 PIRQ1 .................................................... default 1 KEYLOCK 0 PIRQ0 / GPI20 Selection (Pin H5) 0 PIRQ0 .................................................... default 1 GPI20
Offset 55 - PNP IRQ Routing 1 ........................................ RW 7-4 PIRQA# Routing (see PnP IRQ routing table) 3-0 PIRQ0 Routing (see PnP IRQ routing table) Offset 56 - PNP IRQ Routing 2 ........................................ RW 7-4 PIRQC# Routing (see PnP IRQ routing table) 3-0 PIRQB# Routing (see PnP IRQ routing table) Offset 57 - PNP IRQ Routing 3 ........................................ RW 7-4 PIRQD# Routing (see PnP IRQ routing table) 3-0 PIRQ1 Routing (see PnP IRQ routing table)
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7HFKQRORJLHV ,QF
:H &RQQHFW
VT82C596B
Offset 5B - Internal RTC Test Mode .............................. RW ........................................always reads 0 7-4 Reserved 3 RTC Map Rx32 to Rx7F Century Byte 0 Disable................................................... default 1 Enable 2 RTC Reset Enable (do not program) ..........default=0 1 RTC SRAM Access Enable 0 Disable................................................... default 1 Enable This bit is set if the internal RTC is disabled but it is desired to still be able to access the internal RTC SRAM via ports 74-75. If the internal RTC is enabled, setting this bit does nothing (the internal RTC SRAM should be accessed at either ports 70/71 or 72/73. 0 RTC Test Mode Enable (do not program) .default=0 Offset 5C - DMA Control................................................. RW 7 Gate Port 61 Command Output 0 Disable................................................... default 1 Enable 6 Passive Release 0 Disable................................................... default 1 Enable 5 Internal Passive Release 0 Disable................................................... default 1 Enable 4 Dummy Request 0 Disable................................................... default 1 Enable 3 Extended DMA Command and TC 0 Disable................................................... default 1 Enable 2 External APIC Configuration 0 External APIC on XD Bus..................... default 1 External APIC on SD Bus (disable XOE# for APIC cycles) ........................................always reads 0 1 Reserved 0 DMA Line Buffer Disable 0 DMA cycles can be to/from line buffer ....... def 1 Disable DMA Line Buffer
Offset 5A - KBC / RTC Control ...................................... RW Bits 7-4 of this register are latched from pins SD7-4 at powerup but are read/write accessible so may be changed after power-up to change the default strap setting: 7 6 5 4 3 2 Keyboard RP16 ............................. latched from SD7 Keyboard RP15 ............................ latched from SD6 Keyboard RP14 ............................ latched from SD5 Keyboard RP13 ............................ latched from SD4 ....................................... always reads 0 Reserved Internal RTC Enable 0 Disable 1 Enable ....................................................default Internal PS2 Mouse Enable 0 Disable ..................................................default 1 Enable Internal KBC Enable 0 Disable ..................................................default 1 Enable External strap option values may be set by connecting the indicated external pin to a 4.7K ohm pullup (for 1) or driving it low during reset with a 7407 TTL open collector buffer (for 0) as shown in the suggested circuit below:
9&& 5(6(7 9&& . 6'Q
1
0
Note:
Figure 5. Strap Option Circuit
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7HFKQRORJLHV ,QF
:H &RQQHFW
VT82C596B
Distributed DMA / Serial IRQ Control Offset 61-60 - Distributed DMA Ch 0 Base / Enable ...... RW 15-4 Channel 0 Base Address Bits 15-4 .......... default = 0 3 Channel 0 Enable 0 Disable ...................................................default 1 Enable ........................................ always reads 0 2-0 Reserved Offset 63-62 - Distributed DMA Ch 1 Base / Enable ...... RW 15-4 Channel 1 Base Address Bits 15-4 .......... default = 0 3 Channel 1 Enable 0 Disable ...................................................default 1 Enable ........................................ always reads 0 2-0 Reserved Offset 65-64 - Distributed DMA Ch 2 Base / Enable ...... RW 15-4 Channel 2 Base Address Bits 15-4 .......... default = 0 3 Channel 2 Enable 0 Disable ...................................................default 1 Enable ........................................ always reads 0 2-0 Reserved Offset 67-66 - Distributed DMA Ch 3 Base / Enable ...... RW 15-4 Channel 3 Base Address Bits 15-4 .......... default = 0 3 Channel 3 Enable 0 Disable ...................................................default 1 Enable ........................................ always reads 0 2-0 Reserved Offset 69-68 - Serial IRQ Control ................................... RW ........................................ always reads 0 15-4 Reserved 3 Serial IRQ Enable 0 Disable ...................................................default 1 Enable 2 Serial IRQ Mode 0 Continuous Mode ...................................default 1 Quiet Mode 1-0 Start-Frame Width 00 4 PCI Clocks ..........................................default 01 6 PCI Clocks 10 8 PCI Clocks 11 -reservedThe frame size is fixed at 21 PCI clocks. Offset 6B-6A - Distributed DMA Ch 5 Base / Enable.... RW 15-4 Channel 5 Base Address Bits 15-4...........default = 0 3 Channel 5 Enable 0 Disable................................................... default 1 Enable ........................................always reads 0 2-0 Reserved Offset 6D-6C - Distributed DMA Ch 6 Base / Enable ... RW 15-4 Channel 6 Base Address Bits 15-4...........default = 0 3 Channel 6 Enable 0 Disable................................................... default 1 Enable ........................................always reads 0 2-0 Reserved Offset 6F-6E - Distributed DMA Ch 7 Base / Enable .... RW 15-4 Channel 7 Base Address Bits 15-4...........default = 0 3 Channel 7 Enable 0 Disable................................................... default 1 Enable ........................................always reads 0 2-0 Reserved
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VT82C596B
Miscellaneous / General Purpose I/O Offset 73-70 - Subsystem ID ............................................ WO 31-0 Subsystem ID and Subsystem Vendor ID Write Only. Always reads back 0. Contents may be read at offset 2C. Offset 77-74 - GPIO / Chip Select Control ..................... RW ........................................ always reads 0 31-30 Reserved 29 PCS1# For Internal I/O (Pin N5) 0 Disable ...................................................default 1 Enable 28 PCS0# For Internal I/O (Pin L4) 0 Disable ...................................................default 1 Enable 27 RTC Rx32 Remap to Rx7F Century Byte 0 Disable ...................................................default 1 Enable 26 RTC Rx32 Write Protect 0 Disable ...................................................default 1 Enable 25 RTC Rx0D Write Protect 0 Disable ...................................................default 1 Enable 24 DMA Controller Shadow Registers 0 Disable ...................................................default 1 Enable ........................................ always reads 0 23-22 Reserved 21 PCS1# Enable (Pin N5) 0 Disable ...................................................default 1 Enable 20 PCS0# Enable (Pin L4) 0 Disable ...................................................default 1 Enable 19 MCCS# Enable (Pin N4) 0 Disable ...................................................default 1 Enable 18 GPO26 Enable (Pin K1) 0 Disable ...................................................default 1 Enable 17 GPO25 Enable (Pin L1) 0 Disable ...................................................default 1 Enable 16 GPO24 Enable (Pin M2) 0 Disable ...................................................default 1 Enable 15 GPO23 Enable (Pin M4) 0 Disable ...................................................default 1 Enable 14 GPO22 Enable (Pin M3) 0 Disable ...................................................default 1 Enable
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GPO21 Enable 0 Disable................................................... default 1 Enable GPO20 Enable 0 Disable................................................... default 1 Enable GPO19 Enable (Pin K16) 0 Disable................................................... default 1 Enable GPO18 Enable (Pin R2) 0 Disable................................................... default 1 Enable GPO17 Enable (Pin R1) 0 Disable................................................... default 1 Enable Decode 0 Subtractive ............................................. default 1 Positive APIC Enable 0 Disable................................................... default 1 Enable GPI12 Enable (Pin P18) 0 Disable................................................... default 1 Enable GPI11 Enable (Pin N17) 0 Disable................................................... default 1 Enable GPI10 Enable (Pin P16) 0 Disable................................................... default 1 Enable GPI9 Enable (Pin U19) 0 Disable................................................... default 1 Enable GPI8 Enable (Pin H19) 0 Disable................................................... default 1 Enable Internal APIC 0 Disable................................................... default 1 Enable GPI0/IOCHCK, GPO[7-1]/LA[23-17] Select 0 GPI0, GPO[7-1]..................................... default 1 IOCHCK, LA[23-17]
Bits 18-0 also control multi-function pin definitions. Refer to the General Purpose Inputs and Outputs sections of the pin descriptions for more information.
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7HFKQRORJLHV ,QF
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VT82C596B
Offset 80 - Programmable Chip Select Mask ................ RW 7-4 PCS1 I/O Port Address Mask bits 3-0 3-0 PCS0 I/O Port Address Mask bits 3-0
Offset 7B-78 - Programmable Chip Select Control ....... RW 31-16 PCS1 I/O Port Address [15-0] 15-0 PCS0 I/O Port Address [15-0] Offset 7F-7C - PC/PCI Control ....................................... RW ........................................ always reads 0 31-11 Reserved 10 PCI DMA Pair C Enable 0 Disable ...................................................default 1 Enable 9 PCI DMA Pair B Enable 0 Disable ...................................................default 1 Enable 8 PCI DMA Pair A Enable 0 Disable ...................................................default 1 Enable 7 PCI DMA Channel 7 Enable 0 Disable ...................................................default 1 Enable 6 PCI DMA Channel 6 Enable 0 Disable ...................................................default 1 Enable 5 PCI DMA Channel 5 Enable 0 Disable ...................................................default 1 Enable ........................................ always reads 0 4 Reserved 3 PCI DMA Channel 3 Enable 0 Disable ...................................................default 1 Enable 2 PCI DMA Channel 2 Enable 0 Disable ...................................................default 1 Enable 1 PCI DMA Channel 1 Enable 0 Disable ...................................................default 1 Enable 0 PCI DMA Channel 0 Enable 0 Disable ...................................................default 1 Enable
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7HFKQRORJLHV ,QF
:H &RQQHFW
VT82C596B
Offset 82 - ISA Positive Decoding Control 2 .................. RW 7 FDC Positive Decoding 0 Disable................................................... default 1 Enable 6 LPT Positive Decoding 0 Disable................................................... default 1 Enable 5-4 LPT Decode Range 00 3BCh-3BFh, 7BCh-7BEh ...................... default 01 378h-37Fh, 778h-77Ah 10 278h-27Fh, 678h-67Ah 11 -reserved3 Game Port Positive Decoding 0 Disable................................................... default 1 Enable 2 MIDI Positive Decoding 0 Disable................................................... default 1 Enable 1-0 MIDI Decode Range 00 300h-303h.............................................. default 01 310h-313h 10 320h-323h 11 330h-333h
Offset 81 - ISA Positive Decoding Control 1 .................. RW 7 On-Board I/O Port Positive Decoding 0 Disable ...................................................default 1 Enable 6 Microsoft-Sound System I/O Port Positive Decoding 0 Disable ...................................................default 1 Enable 5-4 Microsoft-Sound System I/O Decode Range 00 0530h-0537h ..........................................default 01 0604h-060Bh 10 0E80-0E87h 11 0F40h-0F47h 3 APIC Positive Decoding 0 Disable ...................................................default 1 Enable 2 BIOS ROM Positive Decoding 0 Disable ...................................................default 1 Enable 1 PCS1 Positive Decoding 0 Disable ...................................................default 1 Enable 0 PCS0 Positive Decoding 0 Disable ...................................................default 1 Enable
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7HFKQRORJLHV ,QF
:H &RQQHFW
VT82C596B
Offset 84 - ISA Positive Decoding Control 4 .................. RW ........................................always reads 0 7-4 Reserved 3 FDC Decoding Range 0 Primary .................................................. default 1 Secondary 2 Sound Blaster Positive Decoding 0 Disable................................................... default 1 Enable 1-0 Sound Blaster Decode Range 00 220h-22Fh, 230h-233h .......................... default 01 240h-24Fh, 250h-253h 10 260h-26Fh, 270h-273h 11 280h-28Fh, 290h-293h
Offset 83 - ISA Positive Decoding Control 3 .................. RW 7 COM Port B Positive Decoding 0 Disable ...................................................default 1 Enable 6-4 COM-Port B Decode Range 000 3F8h-3FFh (COM1) ............................default 001 2F8h-2FFh (COM2) 010 220h-227h 011 228h-22Fh 100 238h-23Fh 101 2E8h-2EFh (COM4) 110 338h-33Fh 111 3E8h-3EFh (COM3) 3 COM Port A Positive Decoding 0 Disable ...................................................default 1 Enable 2-0 COM-Port A Decode Range 000 3F8h-3FFh (COM1) ............................default 001 2F8h-2FFh (COM2) 010 220h-227h 011 228h-22Fh 100 238h-23Fh 101 2E8h-2EFh (COM4) 110 338h-33Fh 111 3E8h-3EFh (COM3)
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VT82C596B
Offset 89 - PLL Control ................................................... RW ........................................always reads 0 7-4 Reserved 3-2 PLL PCLK Input Delay Select 1-0 PLL CLK66 Feedback Delay Select
Offset 87 - Test 1 ............................................................... RW 7 UltraDMA-66 Test 0 Disable ...................................................default 1 Enable 6 USB Port Test 0 Disable ...................................................default 1 Enable 5-4 USB Port Test Select ........................................ always reads 0 3-0 Reserved
Offset 88 - Test 2 ............................................................... RW ........................................ always reads 0 7-5 Reserved 4 PLL PU 0 Enable.....................................................default 1 Disable 3 PLL Test Mode 0 Disable ...................................................default 1 Enable 2-0 PLL Test Mode Select
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7HFKQRORJLHV ,QF
:H &RQQHFW
VT82C596B
Offset 9 - Programming Interface ................................... RW 7 Master IDE Capability........... fixed at 1 (Supported) ........................................always reads 0 6-4 Reserved 3 Programmable Indicator - Secondary ...... fixed at 1 Supports both modes (may be set to either mode by writing bit-2) 2 Channel Operating Mode - Secondary 0 Compatibility Mode (fixed addressing) 1 Native PCI Mode (flexible addressing) ....... def 1 Programmable Indicator - Primary.......... fixed at 1 Supports both modes (may be set to either mode by writing bit-0) 0 Channel Operating Mode - Primary 0 Compatibility Mode (fixed addressing) 1 Native PCI Mode (flexible addressing) ....... def Compatibility Mode (fixed IRQs and I/O addresses): Command Block Control Block Registers IRQ Channel Registers Pri 1F0-1F7 3F6 14 Sec 170-177 376 15 Native PCI Mode (registers are programmable in I/O space) Command Block Control Block Registers Channel Registers Pri BA @offset 10h BA @offset 14h Sec BA @offset 18h BA @offset 1Ch Command register blocks are 8 bytes of I/O space Control registers are 4 bytes of I/O space (only byte 2 is used) Offset A - Sub Class Code (01h=IDE Controller) ........... RO Offset B - Base Class Code (01h=Mass Storage Ctrlr) ... RO Offset D - Latency Timer (00h) ....................................... RW 7-4 Latency Timer.............................................default=0 ........................................always reads 0 3-0 Reserved Offset E - Header Type (00h)............................................ RO Offset F - BIST (00h) ......................................................... RO
Function 1 Registers - Enhanced IDE Controller This Enhanced IDE controller interface is fully compatible with the SFF 8038i v.1.0 specification. There are two sets of software accessible registers -- PCI configuration registers and Bus Master IDE I/O registers. The PCI configuration registers are located in the function 1 PCI configuration space of the VT82C596B. The Bus Master IDE I/O registers are defined in the SFF8038i v1.0 specification. PCI Configuration Space Header Offset 1-0 - Vendor ID (1106h=VIA) ................................RO Offset 3-2 - Device ID (0571h=IDE Controller) ...............RO Offset 5-4 - Command ....................................................... RW ........................................ always reads 0 15-10 Reserved 9 Fast Back to Back Cycles ..........fixed at 0 (disabled) 8 SERR# Enable............................fixed at 0 (disabled) 7 Address Stepping ...................... default=1 (enabled) VIA recommends that this bit always be set to 1 to provide additional address decode time to IDE devices. 6 Parity Error Response...............fixed at 0 (disabled) 5 VGA Palette Snoop ....................fixed at 0 (disabled) 4 Memory Write & Invalidate .....fixed at 0 (disabled) 3 Special Cycles .............................fixed at 0 (disabled) 2 Bus Master ............................. default = 0 (disabled) S/G operation can be issued only when the "Bus Master" bit is enabled. 1 Memory Space............................fixed at 0 (disabled) 0 I/O Space ............................. default = 0 (disabled) When the "I/O Space" bit is disabled, the device will not respond to any I/O addresses for both compatible and native mode. Offset 7-6 - Status ........................................................... RWC 15 Detected Parity Error ................................ default=0 14 Signalled System Error.............................. default=0 13 Received Master Abort.............................. default=0 12 Received Target Abort .............................. default=0 11 Signalled Target Abort ..............................Fixed at 0 10-9 DEVSEL# Timing ..................default = 01 (medium) 8 Data Parity Detected.................................. default=0 7 Fast Back to Back ......................................Fixed at 1 ........................................ always reads 0 6-0 Reserved Offset 8 - Revision ID .........................................................RO 0-7 Revision Code for IDE Controller Logic Block
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Function 1 Registers - Enhanced IDE Controller
7HFKQRORJLHV ,QF
:H &RQQHFW
VT82C596B
Offset 3C - Interrupt Line (0Eh) ..................................... RW Offset 3D - Interrupt Pin (00h) ......................................... RO 7-0 Interrupt Routing Mode 00h Legacy mode interrupt routing............... default 01h Native mode interrupt routing Offset 3E - Min Gnt (00h) ................................................. RO Offset 3F - Max Latency (00h).......................................... RO
Offset 13-10 - Pri Data / Command Base Address.......... RW Specifies an 8 byte I/O address space. ..........................................always read 0 31-16 Reserved 15-3 Port Address....................................... default=01F0h 2-0 Fixed at 001b ..................................................... fixed Offset 17-14 - Pri Control / Status Base Address............ RW Specifies a 4 byte I/O address space of which only the third byte is active (i.e., 3F6h for the default base address of 3F4h). ..........................................always read 0 31-16 Reserved 15-2 Port Address....................................... default=03F4h 1-0 Fixed at 01b ....................................................... fixed Offset 1B-18 - Sec Data / Command Base Address ........ RW Specifies an 8 byte I/O address space. ..........................................always read 0 31-16 Reserved 15-3 Port Address ...................................... default=0170h 2-0 Fixed at 001b ..................................................... fixed Offset 1F-1C - Sec Control / Status Base Address .......... RW Specifies a 4 byte I/O address space of which only the third byte is active (i.e., 376h for the default base address of 374h). ..........................................always read 0 31-16 Reserved 15-2 Port Address ...................................... default=0374h 1-0 Fixed at 01b ....................................................... fixed Offset 23-20 - Bus Master Control Regs Base Address .. RW Specifies a 16 byte I/O address space compliant with the SFF8038i rev 1.0 specification. ..........................................always read 0 31-16 Reserved 15-4 Port Address ....................................... default=CC0h 3-0 Fixed at 0001b .................................................. fixed
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Function 1 Registers - Enhanced IDE Controller
7HFKQRORJLHV ,QF
:H &RQQHFW
VT82C596B
IDE-Controller-Specific Confiiguration Registers Offset 40 - Chip Enable..................................................... RW ........................................ always reads 0 7-4 Reserved 3-2 Reserved (Do Not Program)...........R/W, default = 0 1 Primary Channel Enable........ default = 0 (disabled) 0 Secondary Channel Enable .... default = 0 (disabled) Offset 41 - IDE Configuration .......................................... RW 7 Primary IDE Read Prefetch Buffer 0 Disable ...................................................default 1 Enable 6 Primary IDE Post Write Buffer 0 Disable ...................................................default 1 Enable 5 Secondary IDE Read Prefetch Buffer 0 Disable ...................................................default 1 Enable 4 Secondary IDE Post Write Buffer 0 Disable ...................................................default 1 Enable 3 Reserved (Do Not Change)........................ default=0 2 Reserved (Do Not Change)........................ default=1 1 Reserved (Do Not Change)........................ default=1 0 Reserved (Do Not Change)........................ default=0 Offset 42 - Reserved (Do Not Program) .......................... RW ........................................ always reads 0 7-2 Reserved 1-0 Reserved (Do Not Program).................... default = 0 Offset 43 - FIFO Configuration ....................................... RW ........................................always reads 0 7-4 Reserved 3-2 Threshold for Primary Channel 00 1 01 1/4 10 1/2 .................................................... default 11 3/4 1-0 Threshold for Secondary Channel 00 1 01 1/4 10 1/2 .................................................... default 11 3/4
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7HFKQRORJLHV ,QF
:H &RQQHFW
VT82C596B
Offset 46 - Miscellaneous Control 3 ................................ RW 7 Primary Channel Read DMA FIFO Flush 1 = Enable FIFO flush for read DMA when interrupt asserts primary channel. ...............default=1 (enabled) 6 Secondary Channel Read DMA FIFO Flush 1 = Enable FIFO flush for Read DMA when interrupt asserts secondary channel. ........... Default=1 (enabled) 5 Primary Channel End-of-Sector FIFO Flush 1 = Enable FIFO flush at the end of each sector for the primary channel. ................... Default=0 (disabled) 4 Secondary Channel End-of-Sector FIFO Flush 1 = Enable FIFO flush at the end of each sector for the secondary channel................. Default=0 (disabled) ........................................always reads 0 3-2 Reserved 1-0 Max DRDY Pulse Width Maximum DRDY# pulse width after the cycle count. Command will deassert in spite of DRDY# status to avoid system ready hang. 00 No limitation.......................................... default 01 64 PCI clocks 10 128 PCI clocks 11 192 PCI clocks
Offset 44 - Miscellaneous Control 1 ................................. RW ........................................ always reads 0 7 Reserved 6 Master Read Cycle IRDY# Wait States 0 0 wait states 1 1 wait state..............................................default 5 Master Write Cycle IRDY# Wait States 0 0 wait states 1 1 wait state..............................................default 4 Reserved (Do Not Program)...........R/W, default = 0 3 Bus Master IDE Status Register Read Retry Retry bus master IDE status register read when master write operation for DMA read is not complete 0 Disabled 1 Enabled...................................................default 2-1 Reserved (Do Not Program)...........R/W, default = 0 0 UltraDMA Host Must Wait for First Strobe Before Termination 0 Enabled...................................................default 1 Disabled Offset 45 - Miscellaneous Control 2 ................................. RW ........................................ always reads 0 7 Reserved 6 Interrupt Steering Swap 0 Don't swap channel interrupts................default 1 Swap interrupts between the two channels ........................................ always reads 0 5-4 Reserved 3 Memory Read Multiple Command 0 Disable ...................................................default 1 Enable 2 Memory Read and Invalidate Command 0 Disable ...................................................default 1 Enable 1 Secondary Channel Threshold Enable 0 Disable (data transfer starts immediately if FIFO is not empty) 1 Enable (data transfer will not start until the FIFO is filled to the threshold set in bits 1-0 of Rx43) .....................................................default 0 Primary Channel Threshold Enable 0 Disable (data transfer starts immediately if FIFO is not empty) 1 Enable (data transfer will not start until the FIFO is filled to the threshold set in bits 3-2 of Rx43) .....................................................default
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Function 1 Registers - Enhanced IDE Controller
7HFKQRORJLHV ,QF
:H &RQQHFW
VT82C596B
Offset 53-50 - UltraDMA Extended Timing Control ..... RW 31 Pri Drive 0 UltraDMA-Mode Enable Method 0 Enable by using "Set Feature" command..... def 1 Enable by setting bit-30 of this register 30 Pri Drive 0 UltraDMA-Mode Enable 0 Disable................................................... default 1 Enable UltraDMA-Mode Operation 29 Pri Drive 0 Transfer Mode 0 Based on DMA or PIO Mode ............... default 1 Based on UltraDMA Mode ........................................always reads 0 28-26 Reserved 25-24 Pri Drive 0 Cycle Time (T = 30nsec @33MHz) 00 2T 01 3T 10 4T 11 5T .................................................... default Pri Drive 1 UltraDMA-Mode Enable Method Pri Drive 1 UltraDMA-Mode Enable Pri Drive 1 Transfer Mode ........................................always reads 0 Reserved Pri Clock Source 0 33 MHz.................................................. default 1 66 MHz ........................................always reads 0 18 Reserved 17-16 Pri Drive 1 Cycle Time 15 14 13 12-10 9-8 7 6 5 4 3 Sec Drive 0 UltraDMA-Mode Enable Method Sec Drive 0 UltraDMA-Mode Enable Sec Drive 0 Transfer Mode ........................................always reads 0 Reserved Sec Drive 0 Cycle Time Sec Drive 1 UltraDMA-Mode Enable Method Sec Drive 1 UltraDMA-Mode Enable Sec Drive 1 Transfer Mode ........................................always reads 0 Reserved Sec Clock Source 0 33 MHz.................................................. default 1 66 MHz ........................................always reads 0 Reserved Sec Drive 1 Cycle Time 23 22 21 20 19
Offset 4B-48 - Drive Timing Control ............................... RW The following fields define the Active Pulse Width and Recovery Time for the IDE DIOR# and DIOW# signals: 31-28 Primary Drive 0 Active Pulse Width...... def=1010b 27-24 Primary Drive 0 Recovery Time ............. def=1000b 23-20 Primary Drive 1 Active Pulse Width...... def=1010b 19-16 Primary Drive 1 Recovery Time ............. def=1000b 15-12 Secondary Drive 0 Active Pulse Width .. def=1010b 11-8 Secondary Drive 0 Recovery Time ......... def=1000b 7-4 Secondary Drive 1 Active Pulse Width .. def=1010b 3-0 Secondary Drive 1 Recovery Time ......... def=1000b The actual value for each field is the encoded value in the field plus one and indicates the number of PCI clocks. Offset 4C - Address Setup Time ....................................... RW 7-6 Primary Drive 0 Address Setup Time 5-4 Primary Drive 1 Address Setup Time 3-2 Secondary Drive 0 Address Setup Time 1-0 Secondary Drive 1 Address Setup Time For each field above: 00 1T 01 2T 10 3T 11 4T .....................................................default Offset 4E - Secondary Non-1F0 Port Access Timing...... RW 7-4 DIOR#/DIOW# Active Pulse Width....... def=1111b 3-0 DIOR#/DIOW# Recovery Time.............. def=1111b The actual value for each field is the encoded value in the field plus one and indicates the number of PCI clocks. Offset 4F - Primary Non-1F0 Port Access Timing ........ RW 7-4 DIOR#/DIOW# Active Pulse Width....... def=1111b 3-0 DIOR#/DIOW# Recovery Time.............. def=1111b The actual value for each field is the encoded value in the field plus one and indicates the number of PCI clocks.
2 1-0
Each byte defines UltraDMA operation for the indicated drive. The bit definitions are the same within each byte.
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:H &RQQHFW
VT82C596B
Offset 61-60 - Primary Sector Size .................................. RW ........................................always reads 0 15-12 Reserved 11-0 Number of Bytes Per Sector ................ default=200h Offset 69-68 - Secondary Sector Size .............................. RW ........................................always reads 0 15-12 Reserved 11-0 Number of Bytes Per Sector ...def=200h (512 bytes)
Offset 54 - UltraDMA FIFO Control .............................. RW 7-5 Reserved (Do Not Program).............. RW, default=0 4 Split REQ Change Channel 0 Enable ....................................................default 1 Disable ........................................ always reads 0 3 Reserved 2 Change Drive to Clear All FIFO & Internal States 0 Disabled 1 Enabled ..................................................default 1 Add Dummy FIFO Push After End of Transfer 0 Enabled 1 Disabled ................................................default This bit is normally set to 0 for effective handling of transfer lengths that are not doubleword multiples 0 Complete DMA Cycle with Transfer Size Less Than FIFO Size 0 Enabled...................................................default 1 Disabled
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Offset 78 - Secondary IDE Status ................................... RW 7 Interrupt Status 6 Prefetch Buffer Status 5 Post Write Buffer Status 4 DMA Read Prefetch Status 3 DMA Write Prefetch Status 2 S/G Operation Complete ........................................always reads 0 1-0 Reserved Offset 79 - Secondary Interrupt Control ........................ RW ........................................always reads 0 7-1 Reserved 0 Flush FIFO Before Generating IDE Interrupt 0 Desable .................................................. default 1 Enable Offset 7C - Secondary IDE Command 1 ........................ RW 7 Reload Sector Size After Last Command Register Write ........................................always reads 0 6-0 Reserved Offset 7D - Secondary IDE Command 2 ........................ RW 7 Set Controller to Perform PIO Mode Data Port Prefetch 6 Set Controller to Perform PIO Mode Data Port Buffer Write 5 Set Controller to Perform DMA Mode Read Pipeline Operation 4 Set Controller to Perform DMA Mode Write Pipeline Operation 3 Stop S/G Bus Master ........................................always reads 0 2-0 Reserved
Offset 70 - Primary IDE Status ....................................... RW 7 Interrupt Status 6 Prefetch Buffer Status 5 Post Write Buffer Status 4 DMA Read Prefetch Status 3 DMA Write Prefetch Status 2 S/G Operation Complete ........................................ always reads 0 1-0 Reserved Offset 71 - Primary Interrupt Control............................ RW ........................................ always reads 0 7-1 Reserved 0 Flush FIFO Before Generating IDE Interrupt 0 Desable...................................................default 1 Enable Offset 74 - Primary IDE Command 1 ............................. RW 7 Reload Sector Size After Last Command Register Write ........................................ always reads 0 6-0 Reserved Offset 75 - Primary IDE Command 2 ............................. RW 7 Set Controller to Perform PIO Mode Data Port Prefetch 6 Set Controller to Perform PIO Mode Data Port Buffer Write 5 Set Controller to Perform DMA Mode Read Pipeline Operation 4 Set Controller to Perform DMA Mode Write Pipeline Operation 3 Stop S/G Bus Master ........................................ always reads 0 2-0 Reserved
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IDE I/O Registers These registers are compliant with the SFF 8038I v1.0 standard. Refer to the SFF 8038I v1.0 specification for further details. I/O Offset 0 - Primary Channel Command I/O Offset 2 - Primary Channel Status I/O Offset 4-7 - Primary Channel PRD Table Address
Offset 83-80 - Primary S/G Descriptor Address ............ RW Offset 8B-88 - Secondary S/G Descriptor Address ........ RW
I/O Offset 8 - Secondary Channel Command I/O Offset A - Secondary Channel Status I/O Offset C-F - Secondary Channel PRD Table Address
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Offset 8 - Revision ID (nnh) .............................................. RO 7-0 Silicon Revision Code (0 indicates first silicon) Offset 9 - Programming Interface (00h) .......................... RO Offset A - Sub Class Code (03h) ....................................... RO Offset B - Base Class Code (0Ch) ..................................... RO Offset 0D - Latency Timer ............................................... RW 7-0 Timer Value .......................................... default = 16h Offset 0E - Header Type (00h).......................................... RO Offset 23-20 - USB I/O Register Base Address............... RW ........................................always reads 0 31-16 Reserved 15-5 USB I/O Register Base Address. Port Address for the base of the 32-byte USB I/O Register block, corresponding to AD[15:5] 4-0 00001b Offset 3C - Interrupt Line (00h) ...................................... RW ........................................always reads 0 7-4 Reserved 3-0 USB Interrupt Routing ........................ default = 16h 0000 Disabled................................................. default 0001 IRQ1 0010 Reserved 0011 IRQ3 0100 IRQ4 0101 IRQ5 0110 IRQ6 0111 IRQ7 1000 IRQ8 1001 IRQ9 1010 IRQ10 1011 IRQ11 1100 IRQ12 1101 IRQ13 1110 IRQ14 1111 Disabled Offset 3D - Interrupt Pin (04h) ......................................... RO
Function 2 Registers - Universal Serial Bus Controller This USB host controller interface is fully compatible with UHCI specification v1.1. There are two sets of software accessible registers: PCI configuration registers and USB I/O registers. The PCI configuration registers are located in the function 2 PCI configuration space of the VT82C596B. The USB I/O registers are defined in the UHCI v1.1 specification. PCI Configuration Space Header Offset 1-0 - Vendor ID .......................................................RO 0-7 Vendor ID ................. (1106h = VIA Technologies) Offset 3-2 - Device ID .........................................................RO 0-7 Device ID (3038h = VT82C596B USB Controller) Offset 5-4 - Command ....................................................... RW ........................................ always reads 0 15-8 Reserved 7 Address Stepping ...................... default=0 (disabled) 6 Reserved (parity error response) ..................fixed at 0 5 Reserved (VGA palette snoop) ....................fixed at 0 4 Memory Write and Invalidate . default=0 (disabled) 3 Reserved (special cycle monitoring) ............fixed at 0 2 Bus Master ............................... default=0 (disabled) 1 Memory Space........................... default=0 (disabled) 0 I/O Space ............................... default=0 (disabled) Offset 7-6 - Status ........................................................... RWC 15 Reserved (detected parity error).......... always reads 0 14 Signalled System Error.............................. default=0 13 Received Master Abort.............................. default=0 12 Received Target Abort .............................. default=0 11 Signalled Target Abort .............................. default=0 10-9 DEVSEL# Timing 00 Fast 01 Medium ......................................default (fixed) 10 Slow 11 Reserved ........................................ always reads 0 8-0 Reserved
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USB-Specific Configuration Registers Offset 40 - Miscellaneous Control 1 ................................. RW 7 PCI Memory Command Option 0 Support Memory-Read-Line, Memory-ReadMultiple, and Memory-Write-and-Invalidate .... .....................................................default 1 Only support Memory Read, Memory Write Commands 6 Babble Option 0 Automatically disable babbled port when EOF babble occurs..........................................default 1 Don't disable babbled port 5 PCI Parity Check Option 0 Disable PERR# generation.....................default 1 Enable parity check and PERR# generation ........................................ always reads 0 4 Reserved 3 USB Data Length Option 0 Support TD length up to 1280................default 1 Support TD length up to 1023 2 USB Power Management 0 Disable USB power management...........default 1 Enable USB power management 1 DMA Option 0 16 DW burst access................................default 1 8 DW burst access 0 PCI Wait States 0 Zero wait ................................................default 1 One wait Offset 41 - Miscellaneous Control 2 ................................ RW 7 USB 1.1 Improvement for EOP 0 USB Specification 1.1 Compliant.......... default If a bit stuffing error occurs before EOP, the receiver will accept the packet 1 USB Specification 1.0 Compliant If a bit stuffing error occurs before EOP, the receiver will ignore the packet 6 Patch Read / Resume Issue 0 Enable (Fix the Bug) (Normal Setting).. default 1 Disable (when one USB port is in reset or resume status, the controller may not see the device attached at the other USB port) 5 Patch 1 Bit-Time EOP The USB spec says that the device must assert an EOP in at least two bit times. 0 Enable (accept 1 bit-time EOP) ............. default 1 Disable (require 2 bit-time EOP) 4 Hold PCI Request for Successive Accesses 0 Disable 1 Enable .................................................... default Setting this bit to "enable" causes the system to treat the USB request as higher priority 3 Frame Counter Test Mode 0 Disable................................................... default 1 Enable 2 Trap Option 0 Set trap 60/64 status bits only when trap 60/64 enable bits are set................................... default 1 Set trap 60/64 status bits without checking enable bits 1 A20gate Pass Through Option 0 Pass through A20GATE command sequence defined in UHCI .................................... default 1 Don't pass through Write I/O port 64 (ff) ........................................always reads 0 0 Reserved
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USB I/O Registers These registers are compliant with the UHCI v1.1 standard. Refer to the UHCI v1.1 specification for further details. I/O Offset 1-0 - USB Command I/O Offset 3-2 - USB Status I/O Offset 5-4 - USB Interrupt Enable I/O Offset 7-6 - Frame Number I/O Offset B-8 - Frame List Base Address I/O Offset 0C - Start Of Frame Modify I/O Offset 11-10 - Port 1 Status / Control I/O Offset 13-12 - Port 2 Status / Control I/O Offset 1F-14 - Reserved
Offset 60 - Serial Bus Release Number .............................RO 7-0 Release Number.............................. always reads 10h
Offset C1-C0 - Legacy Support .........................................RO 15-0 UHCI v1.1 Compliant ................ always reads 2000h
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Function 3 Registers - Power Management and SMBus This section describes the ACPI (Advanced Configuration and Power Interface) Power Management system of the VT82C596B which includes a System Management Bus (SMBus) interface controller. The power management system of the VT82C596B supports both ACPI and legacy power management functions and is compatible with the APM v1.2 and ACPI v1.0 specifications. PCI Configuration Space Header Offset 1-0 - Vendor ID .......................................................RO 0-7 Vendor ID ................. (1106h = VIA Technologies) Offset 3-2 - Device ID .........................................................RO 0-7 Device ID ................ (3050h = ACPI Power Mgmt) Offset 5-4 - Command ....................................................... RW ........................................ always reads 0 15-8 Reserved 7 Address Stepping ........................................fixed at 0 6 Reserved (parity error response) ..................fixed at 0 5 Reserved (VGA palette snoop) ....................fixed at 0 4 Memory Write and Invalidate ...................fixed at 0 3 Reserved (special cycle monitoring) ............fixed at 0 2 Bus Master .................................................fixed at 0 1 Memory Space.............................................fixed at 0 0 I/O Space .................................................fixed at 0 Offset 7-6 - Status ........................................................... RWC 15 Detected Parity Error ........................ always reads 0 14 Signalled System Error...................... always reads 0 13 Received Master Abort...................... always reads 0 12 Received Target Abort ...................... always reads 0 11 Signalled Target Abort ...................... always reads 0 10-9 DEVSEL# Timing 00 Fast 01 Medium .....................................default (fixed) 10 Slow 11 Reserved 8 Data Parity Detected.......................... always reads 0 7 Fast Back to Back Capable ............... always reads 1 ........................................ always reads 0 6-0 Reserved Offset 8 - Revision ID (nnh) .............................................. RO 7-0 Silicon Revision Code........................... default = 20h Offset 9 - Programming Interface (00h) .......................... RO The value returned by this register may be changed by writing the desired value to PCI Configuration Function 3 offset 61h. Offset A - Sub Class Code (00h) ....................................... RO The value returned by this register may be changed by writing the desired value to PCI Configuration Function 3 offset 62h. Offset B - Base Class Code (00h) ...................................... RO The value returned by this register may be changed by writing the desired value to PCI Configuration Function 3 offset 63h. Offset 0D - Latency Timer ............................................... RW 7-0 Timer Value ..............................................default = 0 Offset 0E - Header Type (00h).......................................... RO
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Power Management-Specific PCI Configuration Registers Offset 40 - Debounce Control ........................................... RW ........................................ always reads 0 7-6 Reserved 5 Debounce LID and PWRBTN# Inputs for 200us 0 Disable ...................................................default 1 Enable ........................................ always reads 0 4-0 Reserved Offset 41 - General Configuration (00h) ......................... RW 7 I/O Enable for ACPI I/O Base 0 Disable access to ACPI I/O block.......... default 1 Allow access to Power Management I/O Register Block (see offset 4B-48 to set the base address for this register block). The definitions of the registers in the Power Management I/O Register Block are included later in this document, following the Power Management Subsystem overview. 6 ACPI Timer Reset 0 Disable................................................... default 1 Enable 5-4 Reserved (Do Not Program) ......................default = 0 3 ACPI Timer Count Select 0 24-bit Timer........................................... default 1 32-bit Timer 2 RTC Enable Signal Gated with PSON (SUSC#) in Soft-Off Mode 0 Disable................................................... default 1 Enable 1 Clock Throttling Clock Selection 0 32 usec (512 usec cycle time) ................ default 1 1 msec (16 msec cycle time) 0 Reserved (Do Not Program) ......................default = 0
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Offset 45-44 - Primary Interrupt Channel (0000h) ....... RW 15 1/0 = Ena/Disa IRQ15 as Primary Intrpt Channel 14 1/0 = Ena/Disa IRQ14 as Primary Intrpt Channel 13 1/0 = Ena/Disa IRQ13 as Primary Intrpt Channel 12 1/0 = Ena/Disa IRQ12 as Primary Intrpt Channel 11 1/0 = Ena/Disa IRQ11 as Primary Intrpt Channel 10 1/0 = Ena/Disa IRQ10 as Primary Intrpt Channel 9 1/0 = Ena/Disa IRQ9 as Primary Intrpt Channel 8 1/0 = Ena/Disa IRQ8 as Primary Intrpt Channel 7 1/0 = Ena/Disa IRQ7 as Primary Intrpt Channel 6 1/0 = Ena/Disa IRQ6 as Primary Intrpt Channel 5 1/0 = Ena/Disa IRQ5 as Primary Intrpt Channel 4 1/0 = Ena/Disa IRQ4 as Primary Intrpt Channel 3 1/0 = Ena/Disa IRQ3 as Primary Intrpt Channel ........................................always reads 0 2 Reserved 1 1/0 = Ena/Disa IRQ1 as Primary Intrpt Channel 0 1/0 = Ena/Disa IRQ0 as Primary Intrpt Channel
Offset 42 - SCI Interrupt Configuration (00h) ............... RW 7 ATX/AT Power Indicator....................................RO 0 ATX .....................................................default 1 AT 6 SUSC State ..........................................................RO ........................................ always reads 0 5 Reserved 4 SUSC Default Off Enable Status ........................RO 3-0 SCI Interrupt Assignment 0000 Disabled .................................................default 0001 IRQ1 0010 Reserved 0011 IRQ3 0100 IRQ4 0101 IRQ5 0110 IRQ6 0111 IRQ7 1000 IRQ8 1001 IRQ9 1010 IRQ10 1011 IRQ11 1100 IRQ12 1101 IRQ13 1110 IRQ14 1111 IRQ15
Offset 47-46 - Secondary Interrupt Channel (0000h) .... RW 15 1/0 = Ena/Disa IRQ15 as Secondary Intr Channel 14 1/0 = Ena/Disa IRQ14 as Secondary Intr Channel 13 1/0 = Ena/Disa IRQ13 as Secondary Intr Channel 12 1/0 = Ena/Disa IRQ12 as Secondary Intr Channel 11 1/0 = Ena/Disa IRQ11 as Secondary Intr Channel 10 1/0 = Ena/Disa IRQ10 as Secondary Intr Channel 9 1/0 = Ena/Disa IRQ9 as Secondary Intr Channel 8 1/0 = Ena/Disa IRQ8 as Secondary Intr Channel 7 1/0 = Ena/Disa IRQ7 as Secondary Intr Channel 6 1/0 = Ena/Disa IRQ6 as Secondary Intr Channel 5 1/0 = Ena/Disa IRQ5 as Secondary Intr Channel 4 1/0 = Ena/Disa IRQ4 as Secondary Intr Channel 3 1/0 = Ena/Disa IRQ3 as Secondary Intr Channel ........................................always reads 0 2 Reserved 1 1/0 = Ena/Disa IRQ1 as Secondary Intr Channel 0 1/0 = Ena/Disa IRQ0 as Secondary Intr Channel
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Offset 4D - Clock Stop Control ....................................... RW ........................................always reads 0 7-3 Reserved 2 Internal Clock Stop for PCI Idle 0 Disable................................................... default 1 Enable 1 Internal Clock Stop During C3 0 Disable................................................... default 1 Enable 0 Internal Clock Stop During Suspend 0 Disable................................................... default 1 Enable
Offset 4B-48 - Power Management I/O Base ................. RW ........................................ always reads 0 31-16 Reserved 15-7 Power Management I/O Register Base Address. Port Address for the base of the 128-byte Power Management I/O Register block, corresponding to AD[15:7]. The "I/O Space" bit at offset 41 bit-7 enables access to this register block. The definitions of the registers in the Power Management I/O Register Block are included later in this document, following the Power-Management-Specific PCI Configuration register descriptions and the Power Management Subsystem overview. 6-0 0000001b Offset 4C - Host Bus Power Management Control........ RW 7-4 Thermal Duty Cycle (THM_DTY) This 4-bit field determines the duty cycle of the STPCLK# signal when the THRM# pin is asserted low. The field is decoded as follows: 0000 Reserved 0001 0-6.25% 0010 6.25-12.50% 0011 18.75-25.00% 0100 31.25-37.50% 0101 37.50-43.75% 0110 43.75-50.00% 0111 50.00-56.25% 1000 56.25-62.50% 1001 62.50-68.75% 1010 68.75-75.00% 1011 75.00-87.50% 1100 75.00-81.25% 1101 81.25-87.50% 1110 87.50-93.75% 1111 93.75-100% ........................................ always reads 0 3-2 Reserved 1 SRAM ZZ 0 Disable ...................................................default 1 Enable (power down the cache SRAM) 0 CPU Stop Grant Cycle Select 0 From Halt and Stop Grant Cycle ............default 1 From Stop Grant Cycle This bit is combined with I/O space Rx2C[3] for controlling the start of STPCLK# assertion during system suspend mode: Rx2C[3] Rx4C[0] Function 3 Function 3 STPCLK# Assertion I/O Space Cfg Space 0 x Immediate 1 0 Wait for CPU Halt / Stop Grant cycle 1 1 Wait for CPU Stop Grant cycle
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3 GP0 Timer Start On setting this bit to 1, the GP0 timer loads the value defined by bits 15-8 of this register and starts counting down. The GP0 timer is reloaded at the occurrence of certain peripheral events enabled in the GP Timer Reload Enable Register (Power Management I/O Space Offset 38h). If no such event occurs and the GP0 timer counts down to zero, then the GP0 Timer Timeout Status bit is set to one (bit-2 of the Global Status register at Power Management Register I/O Space Offset 28h). Additionally, if the GP0 Timer Timeout Enable bit is set (bit-2 of the Global Enable register at Power Management Register I/O Space Offset 2Ah), then an SMI is generated. GP0 Timer Automatic Reload This bit is set to one to enable the GP0 timer to reload automatically after counting down to 0. GP0 Timer Base 00 Disable................................................... default 01 1/16 second 10 1 second 11 1 minute
Offset 53-50 - GP0/1 Timer Control (0000 0000h) ......... RW 31-30 Conserve Mode Timer Count Value 00 1/16 second ............................................default 01 1/8 second 10 1 second 11 1 minute 29 Conserve Mode Status This bit reads 1 when in Conserve Mode 28 Conserve Mode Enable 0 Disable ...................................................default 1 Enable 27-26 Secondary Event Timer Count Value 00 2 milliseconds.........................................default 01 64 milliseconds 10 1/2 second 11 by EOI + 0.25 milliseconds 25 Secondary Event Occurred Status This bit reads 1 to indicate that a secondary event has occurred (to resume the system from suspend) and the secondary event timer is counting down. 24 Secondary Event Timer Enable 0 Disable ...................................................default 1 Enable 23-16 GP1 Timer Count Value (base defined by bits 5-4) Write to load count value; Read to get current count 15-8 GP0 Timer Count Value (base defined by bits 1-0) Write to load count value; Read to get current count 7 GP1 Timer Start On setting this bit to 1, the GP1 timer loads the value defined by bits 23-16 of this register and starts counting down. The GP1 timer is reloaded at the occurrence of certain peripheral events enabled in the GP Timer Reload Enable Register (Power Management I/O Space Offset 38h). If no such event occurs and the GP1 timer counts down to zero, then the GP1 Timer Timeout Status bit is set to one (bit-3 of the Global Status register at Power Management Register I/O Space Offset 28h). Additionally, if the GP1 Timer Timeout Enable bit is set (bit-3 of the Global Enable register at Power Management Register I/O Space Offset 2Ah), then an SMI is generated. GP1 Timer Automatic Reload This bit is set to one to enable the GP1 timer to reload automatically after counting down to 0. GP1 Timer Base 00 Disable ...................................................default 01 1/4 msec 10 1 second 11 1 minute
2
1-0
6
5-4
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Offset 55 - Wakeup Control ............................................ RW ........................................always reads 0 7-1 Reserved 0 USB Wakeup for STR / STD / Soft Off 0 Disable................................................... default 1 Enable
Offset 54 - GPIO Select .................................................... RW 7 GPO21 Pin Function (Pin T18) 0 SUSST2#................................................default 1 GPO21 6 Power Well Output Gating for STR 0 Disable ...................................................default 1 Enable 5 SUSC# Level for STR 0 SUSC# = 1 for STR................................default 1 SUSC# = 0 for STR 4 GPO20 Pin Function (Pin T17) 0 SUSST1#................................................default 1 GPO20 3 GPO15 Pin Function (Pin V19) 0 SUSB#....................................................default 1 GPO15 2 GPO16 Pin Function (Pin U18) 0 SUSC#....................................................default 1 GPO16 1-0 GPO8 Pin Function (Pin T19) 00 GPO8 (ACPI Rx4C[8] ...........................default 01 1 Hz Output 10 2 Hz Output 11 4 Hz Output
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Offset 61 - Programming Interface Read Value ............ WO 7-0 Rx09 Read Value The value returned by the register at offset 9h (Programming Interface) may be changed by writing the desired value to this location.
Offset 5B-58 - GP2/3 Timer Control (0000 0000h) ........ RW ........................................ always reads 0 31-24 Reserved 23-16 GP3 Timer Count Value (base defined by bits 5-4) Write to load count value; Read to get current count 15-8 GP2 Timer Count Value (base defined by bits 1-0) Write to load count value; Read to get current count 7 GP3 Timer Start On setting this bit to 1, the GP3 timer loads the value defined by bits 23-16 of this register and starts counting down. The GP3 timer is reloaded at the occurrence of certain peripheral events enabled in the GP Timer Reload Enable Register (Power Management I/O Space Offset 38h). If no such event occurs and the GP3 timer counts down to zero, then the GP3 Timer Timeout Status bit is set to one (bit-13 of the Global Status register at Power Management Register I/O Space Offset 28h). Additionally, if the GP3 Timer Timeout Enable bit is set (bit-13 of the Global Enable register at Power Management Register I/O Space Offset 2Ah), then an SMI is generated. GP3 Timer Automatic Reload This bit is set to one to enable the GP3 timer to reload automatically after counting down to 0. GP3 Timer Base 00 Disable ...................................................default 01 1/4 msec 10 1 second 11 1 minute GP2 Timer Start On setting this bit to 1, the GP2 timer loads the value defined by bits 15-8 of this register and starts counting down. The GP2 timer is reloaded at the occurrence of certain peripheral events enabled in the GP Timer Reload Enable Register (Power Management I/O Space Offset 38h). If no such event occurs and the GP2 timer counts down to zero, then the GP2 Timer Timeout Status bit is set to one (bit-12 of the Global Status register at Power Management Register I/O Space Offset 28h). Additionally, if the GP2 Timer Timeout Enable bit is set (bit-12 of the Global Enable register at Power Management Register I/O Space Offset 2Ah), then an SMI is generated. GP2 Timer Automatic Reload This bit is set to one to enable the GP2 timer to reload automatically after counting down to 0. GP2 Timer Base 00 Disable ...................................................default 01 1/16 second 10 1 second 11 1 minute
Offset 62 - Sub Class Read Value .................................... WO 7-0 Rx0A Read Value The value returned by the register at offset 0Ah (Sub Class Code) may be changed by writing the desired value to this location.
Offset 63 - Base Class Read Value................................... WO 7-0 Rx0B Read Value The value returned by the register at offset 0Bh (Base Class Code) may be changed by writing the desired value to this location.
6
5-4
3
2
1-0
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System Management Bus-Specific Configuration Registers Offset 93-90 - SMBus I/O Base ........................................ RW .................................... always reads 00h 31-16 Fixed .......................................... default = 00h 15-4 I/O Base ................................ always reads 0001b 3-0 Fixed Offset D2 - SMBus Control .............................................. RW ........................................ always reads 0 7-4 Reserved 3 SMBus Interrupt Select 0 SMI .....................................................default 1 SCI ........................................ always reads 0 2-1 Reserved 0 SMBus Controller Enable 0 Disable ...................................................default 1 Enable Offset D3 - SMBus Host Slave Command ...................... RW 7-0 SMBus Host Slave Command Code..........default=0 Offset D4 - SMBus Slave Address for Port 1 ................. RW 7-1 SMBus Slave Address for Port 1...............default=0 0 R/W for Shadow Port 1 0 Disable................................................... default 1 Enable Offset D5 - SMBus Slave Address for Port 2 ................. RW 7-1 SMBus Slave Address for Port 2...............default=0 0 R/W for Shadow Port 2 0 Disable................................................... default 1 Enable Offset D6 - SMBus Revision ID ....................................... RO 7-0 SMBus Revision Code
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System Management Bus I/O-Space Registers I/O Offset 00 - SMBus Host Status............................... RWC ........................................ always reads 0 7-5 Reserved 4 Failed Bus Transaction....................................RWC 0 SMBus interrupt not caused by failed bus transaction ..............................................default 1 SMBus interrupt caused by failed bus transaction. This bit may be set when the KILL bit (I/O Rx02[1]) is set and can be cleared by writing a 1 to this bit position. 3 Bus Collision.....................................................RWC 0 SMBus interrupt not caused by transaction collision..................................................default 1 SMBus interrupt caused by transaction collision. This bit is only set by hardware and can be cleared by writing a 1 to this bit position. 2 Device Error .....................................................RWC 0 SMBus interrupt not caused by generation of an SMBus transaction error....................default 1 SMBus interrupt caused by generation of an SMBus transaction error (illegal command field, unclaimed host-initiated cycle, or host device timeout). This bit is only set by hardware and can be cleared by writing a 1 to this bit position. 1 SMBus Interrupt..............................................RWC 0 SMBus interrupt not caused by host command completion..............................................default 1 SMBus interrupt caused by host command completion. This bit is only set by hardware and can be cleared by writing a 1 to this bit position. 0 Host Busy ..........................................................RO 0 SMBus controller host interface is not processing a coimmand ..........................default 1 SMBus host controller is busy processing a coimmand. None of the other SMBus registers should be accessed if this bit is set. I/O Offset 01h - SMBus Slave Status ........................... RWC ........................................always reads 0 7-6 Reserved 5 Alert Status ..................................................... RWC 0 SMBus interrupt not caused by SMBALERT# signal .................................................... default 1 SMBus interrupt caused by SMBALERT# signal. This bit will be set only if the Alert Enable bit is set in the SMBus Slave Control Register at I/O Offset R08[3]. This bit is only set by hardware and can be cleared by writing a 1 to this bit position. 4 Shadow 2 Status............................................... RWC 0 SMBus interrupt not caused by address match to SMBus Shadow Address Port 2......... default 1 SMBus interrupt or resume event caused by slave cycle address match to SMBus Shadow Address Port 2. This bit is only set by hardware and can be cleared by writing a 1 to this bit position. 3 Shadow 1 Status............................................... RWC 0 SMBus interrupt not caused by address match to SMBus Shadow Address Port 1......... default 1 SMBus interrupt or resume event caused by slave cycle address match to SMBus Shadow Address Port 1. This bit is only set by hardware and can be cleared by writing a 1 to this bit position. 2 Slave Status ..................................................... RWC 0 SMBus interrupt not caused by slave event match .................................................... default 1 SMBus interrupt or resume event caused by slave cycle event match of the SMBus Slave Command Register at PCI Function 3 Configuration Offset 85h (command match) and the SMBus Slave Event Register at SMBus Base + Offset 0Ah (data event match). This bit is only set by hardware and can be cleared by writing a 1 to this bit position. ........................................always reads 0 1 Reserved 0 Slave Busy ......................................................... RO 0 SMBus controller slave interface is not processing data ...................................... default 1 SMBus controller slave interface is busy receiving data. None of the other SMBus registers should be accessed if this bit is set.
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I/O Offset 03h - SMBus Host Command ........................ RW 7-0 SMBUS Host Command ..........................default = 0 This field contains the data transmitted in the command field of the SMBus host transaction.
I/O Offset 02h - SMBus Host Control ............................. RW ........................................ always reads 0 7 Reserved ........................................ always reads 0 6 Start 0 Writing 0 has no effect ...........................default 1 Start Execution of Command Writing a 1 to this bit causes the SMBus controller host interface to initiate execution of the command programmed in the SMBus Host Command Register (I/O offset 3). All necessary registers should be programmed prior to writing a 1 to this bit. The Host Busy bit (SMBus Host Status Register bit-0) can be used to identify when the SMBus controller has completed command execution. ........................................ always reads 0 5 Reserved 4-2 SMBus Command Protocol 000 Quick Read or Write ..............................default 001 Byte Read or Write 010 Byte Data Read or Write 011 Word Data Read or Write 100 Reserved 101 Block Read or Write 110 Reserved 111 Reserved 1 Kill 0 Normal host controller operation ...........default 1 Stop the host transaction currently in progress Setting this bit to 1 also sets the FAILED status bit (Host Status bit-4) and asserts the interrupt selected by the SMB Interrupt Select bit (Function 3 SMBus Host Configuration Register Rx84[1]). 0 Interrupt Enable 0 Disable interrupt generation ...................default 1 Enable generation of interrupts on the completion of the current host transaction.
I/O Offset 04h - SMBus Host Address............................ RW The contents of this register are transmitted in the address field of the SMBus host transaction. 7-1 SMBUS Address .......................................default = 0 This field contains the 7-bit address of the targeted slave device. 0 SMBUS Read or Write ............................default = 0 0 Execute a WRITE command ................. default 1 Execute a READ command
I/O Offset 05h - SMBus Host Data 0 .............................. RW The contents of this register are transmitted in the Data 0 field of SMBus host transaction writes. On reads, Data 0 bytes are stored here. 7-0 SMBUS Data 0..........................................default = 0 For Block Write commands, this field is programmed with the block transfer count (a value between 1 and 32). Counts of 0 or greater than 32 are undefined. For Block Read commands, the count received from the SMBus device is stored here. I/O Offset 06h - SMBus Host Data 1 .............................. RW The contents of this register are transmitted in the Data 1 field of SMBus host transaction writes. On reads, Data 1 bytes are stored here. 7-0 SMBUS Data 1..........................................default = 0
I/O Offset 07h - SMBus Block Data ............................... RW Reads and writes to this register are used to access the 32-byte block data storage array. An internal index pointer is used to address the array. It is reset to 0 by reads of the SMBus Host Control register (I/O Offset 2) and incremented automatically by each access to this register. The transfer of block data into (read) or out of (write) this storage array during an SMBus transaction always starts at index address 0. 7-0 SMBUS Block Data ..................................default = 0
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I/O Offset 09h - SMBus Shadow Command ................... RO This register is used to store command values for external SMBus master accesses to the host slave and slave shadow ports. 7-0 Shadow Command....................................default = 0 This field contains the command value which was received during an external SMBus master access whose address field matched the host slave address (10h) or one of the slave shadow port addresses.
I/O Offset 08h - SMBus Slave Control............................ RW ........................................ always reads 0 7-4 Reserved 3 SMBus Alert Enable 0 Disable ...................................................default 1 Enable generation of an interrupt or resume event on the assertion of the SMBALERT# signal 2 SMBus Shadow Port 2 Enable 0 Disable ...................................................default 1 Enable generation of an interrupt or resume event on external SMBus master generation of a transaction with an address that matches the SMBus Slave Shadow Port 2 register (PCI function 3 configuration register Rx87). 1 SMBus Shadow Port 1 Enable 0 Disable ...................................................default 1 Enable generation of an interrupt or resume event on external SMBus master generation of a transaction with an address that matches the SMBus Slave Shadow Port 1 register (PCI function 3 configuration register Rx86). 0 SlaveEnable 0 Disable ...................................................default 1 Enable generation of an interrupt or resume event on external SMBus master generation of a transaction with an address that matches the SMBus host controller slave port of 10h, a command field which matches the SMBus Slave Command register (PCI function 3 configuration register Rx85), and a match of one of the corresponding enabled events in the SMBus Slave Event Register (I/O Offset 0Ah).
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I/O Offset 0Ch - SMBus Slave Data ................................ RO This register is used to store data values for external SMBus master accesses to the shadow ports or the SMBus host controller's slave port. 15-0 SMBus Slave Data ....................................default = 0 This field contains the data value which was transmitted during an external SMBus master access whose address field matched one of the slave shadow port addresses or the SMBus host controller slave port address of 10h.
I/O Offset 0Ah - SMBus Slave Event .............................. RW This register is used to enable generation of interrupt or resume events for accesses to the host controller's slave port. 15-0 SMBus Slave Event .................................. default = 0 This field contains data bits used to compare against incoming data to the SMBus Slave Data Register (I/O Offset 0Ch). When a bit in this register is set and the corresponding bit the Slave Data register is also set, an interrupt or resume event will be generated if the command value matches the value in the SMBus Slave Command register and the access was to SMBus host address 10h.
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Power Management I/O-Space Registers Basic Power Management Control and Status I/O Offset 1-0 - Power Management Status ................. RWC The bits in this register are set only by hardware and can be reset by software by writing a one to the desired bit position. Wakeup Status (WAK_STS) ................... default = 0 This bit is set when the system is in the suspend state and an enabled resume event occurs. Upon setting this bit, the system automatically transitions from the suspend state to the normal working state (from C3 to C0 for the processor). ........................................ always reads 0 14-12 Reserved 11 Power Status (PWR_STS)........................ default = 0 This bit is set by abnormal power off. 10 RTC Status (RTC_STS) ........................... default = 0 This bit is set when the RTC generates an alarm (on assertion of the RTC IRQ signal). 15 9 Sleep Button Status (SB_STS)................. default = 0 This bit is set when the sleep button (SLPBTN# / GPI13) is pressed. Power Button Status (PB_STS)............... default = 0 This bit is set when the PWRBTN# signal is asserted LOW. If the PWRBTN# signal is held LOW for more than four seconds, this bit is cleared and the system will transition into the soft off state. ........................................ always reads 0 Reserved Global Status (GBL_STS)........................ default = 0 This bit is set by hardware when BIOS_RLS is set (typically by an SMI routine to release control of the SCI/SMI lock). When this bit is cleared by software (by writing a one to this bit position) the BIOS_RLS bit is also cleared at the same time by hardware. Bus Master Status (BM_STS) ................. default = 0 This bit is set when a system bus master requests the system bus. All PCI master, ISA master and ISA DMA devices are included. ........................................ always reads 0 Reserved Timer Carry Status (TMR_STS)............. default = 0 The bit is set when the 23rd (31st) bit of the 24 (32) bit ACPI power management timer changes. I/O Offset 3-2 - Power Management Enable .................. RW The bits in this register correspond to the bits in the Power Management Status Register at offset 1-0. 15 Reserved ........................................always reads 0
14-11 Reserved
........................................always reads 0
10
9
8
8
RTC Enable (RTC_EN)............................default = 0 This bit may be set to trigger either an SCI or an SMI (depending on the setting of the SCI_EN bit) to be generated when the RTC_STS bit is set. Sleep Button Enable (SB_EN) .................default = 0 This bit may be set to trigger either an SCI or SMI when the SB_STS bit is set. Power Button Enable (PB_EN) .............. default = 1 This bit may be set to trigger either an SCI or an SMI (depending on the setting of the SCI_EN bit) to be generated when the PB_STS bit is set. ........................................always reads 0 Reserved Global Enable (GBL_EN).........................default = 0 This bit may be set to trigger either an SCI or an SMI (depending on the setting of the SCI_EN bit) to be generated when the GBL_STS bit is set.
7-6 5
7-6 5
4
4
Reserved
........................................always reads 0
3-1 0
3-1 0
........................................always reads 0 Reserved ACPI Timer Enable (TMR_EN) ..............default = 0 This bit may be set to trigger either an SCI or an SMI (depending on the setting of the SCI_EN bit) to be generated when the TMR_STS bit is set.
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I/O Offset 0B-08 - Power Management Timer ............... RW 31-24 Extended Timer Value (ETM_VAL) This field reads back 0 if the 24-bit timer option is selected (Rx41 bit-3). 23-0 Timer Value (TMR_VAL) This read-only field returns the running count of the power management timer. This is a 24/32-bit counter that runs off a 3.579545 MHz clock, and counts while in the S0 (working) system state. The timer is reset to an initial value of zero during a reset, and then continues counting until the 14.31818 MHz input to the chip is stopped. If the clock is restarted without a reset, then the counter will continue counting from where it stopped.
I/O Offset 5-4 - Power Management Control ................. RW ........................................ always reads 0 15-14 Reserved 13 Sleep Enable (SLP_EN)...................... always reads 0 This is a write-only bit; reads from this bit always return zero. Writing a one to this bit causes the system to sequence into the sleep (suspend) state defined by the SLP_TYP field. 12-10 Sleep Type (SLP_TYP) 000 Normal On 001 Suspend to DRAM 010 Suspend to Disk (also called Soft Off). The VCC power plane is turned off while the VCCSUS and VCCRTC planes remain on. 011 Reserved 100 Power On Suspend without Reset 101 Power On Suspend with CPU Reset 110 Power On Suspend with CPU/PCI Reset 111 Reserved In any sleep state, there is minimal interface between powered and non-powered planes so that the effort for hardware design may be well managed. ........................................ always reads 0 9-3 Reserved 2 Global Release (GBL_RLS) ............ WO, default = 0 This bit is set by ACPI software to indicate the release of the SCI / SMI lock. Upon setting of this bit, the hardware automatically sets the BIOS_STS bit. The bit is cleared by hardware when the BIOS_STS bit is cleared by software. Note that the setting of this bit will cause an SMI to be generated if the BIOS_EN bit is set (bit-5 of the Global Enable register at offset 2Ah). 1 Bus Master Reload (BMS_RLD)............. default = 0 This bit is used to enable the occurrence of a bus master request to transition the processor from the C3 state to the C0 state. 0 SCI Enable (SCI_EN)............................... default = 0 Selects the power management event to generate either an SCI or SMI: 0 Generate SMI 1 Generate SCI Note that certain power management events can be programmed individually to generate an SCI or SMI independent of the setting of this bit (refer to the General Purpose SCI Enable and General Purpose SMI Enable registers at offsets 22 and 24). Also, TMR_STS & GBL_STS always generate SCI and BIOS_STS always generates SMI.
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Processor Power Management Registers I/O Offset 13-10 - Processor & PCI Bus Control............ RW ........................................ always reads 0 31-12 Reserved 11 PCI Stop (PCISTP# asserted) when PCKRUN# is Deasserted (PCI_STP) 0 Enable.....................................................default 1 Disable 10 PCI Bus Clock Run Without Stop (PCI_RUN) 0 PCKRUN# will be de-activated after the PCI bus is idle for 26 clocks..........................default 1 PCKRUN# is always asserted 9 Host Clock Stop Enable (HOST_STP) 0 STPCLK# will be asserted in the C3 state, but the CPU clock is not stopped .................default 1 CPU clock is stopped in the C3 state 8 Assertion of SLP# for LVL3 Read 0 Disable ...................................................default 1 Enable Used in Slot-1 systems only. ........................................ always reads 0 7-5 Reserved 4 Throttling Enable (THT_EN). Setting this bit starts clock throttling (modulating the STPCLK# signal) regardless of the CPU state. The throttling duty cycle is determined by bits 3-0 of this register. 3-0 Throttling Duty Cycle (THT_DTY) This 4-bit field determines the duty cycle of the STPCLK# signal when the system is in throttling mode (the "Throttling Enable" bit is set to one). The duty cycle indicates the percentage of time the STPCLK# signal is asserted while the Throttling Enable bit is set. The field is decoded as follows: 0000 Reserved 0001 0-6.25% 0010 6.25-12.50% 0011 18.75-25.00% 0100 31.25-37.50% 0101 37.50-43.75% 0110 43.75-50.00% 0111 50.00-56.25% 1000 56.25-62.50% 1001 62.50-68.75% 1010 68.75-75.00% 1011 75.00-87.50% 1100 75.00-81.25% 1101 81.25-87.50% 1110 87.50-93.75% 1111 93.75-100% I/O Offset 14 - Processor Level 2 (P_LVL2).................... RO ........................................always reads 0 7-0 Level 2 Reads from this register put the processor into the Stop Grant state (the VT82C596B asserts STPCLK# to suspend the processor). Wake up from Stop Grant state is by interrupt (INTR, SMI, and SCI). Reads from this register return all zeros; writes to this register have no effect. I/O Offset 15 - Processor Level 3 (P_LVL3).................... RO ........................................always reads 0 7-0 Level 3 Reads from this register put the processor in the C3 clock state with the STPCLK# signal asserted. If Rx10[9] = 1 then the CPU clock is also stopped by asserting CPUSTP#. Wake up from the C3 state is by interrupt (INTR, SMI, and SCI). Reads from this register return all zeros; writes to this register have no effect.
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General Purpose Power Management Registers I/O Offset 21-20 - General Purpose Status (GP_STS). RWC ........................................ always reads 0 15 Reserved 14 USB Wakeup Status for STR/STD/Soff (UW_STS) ........................................ always reads 0 13 Reserved 12 Battery Low Status (BL_STS) This bit is set when the BATLOW# input is asserted low. 11 Notebook Lid Status (LID_STS) This bit is set when the LID input detects the edge selected by Rx2C bit-7 (0=rising, 1=falling). 10 Thermal Detect Status (THRM_STS) This bit is set when the THRM# input detects the edge selected by Rx2C bit-6 (0=rising, 1=falling). 9 USB Resume Status (USB_STS) This bit is set when a USB peripheral generates a resume event. 8 Ring Status (RI_STS) This bit is set when the RI# input is asserted low. 7 EXTSMI7 Toggle Status (XSMI7_STS) This bit is set when the GPI17 pin is toggled. 6 EXTSMI6 Toggle Status (XSMI6_STS) This bit is set when the GPI16 pin is toggled. 5 EXTSMI5 Toggle Status (XSMI5_STS) This bit is set when the GPI15 pin is toggled. 4 EXTSMI4 Toggle Status (XSMI4_STS) This bit is set when the GPI4 pin is toggled. 3 EXTSMI3 Toggle Status (XSMI3_STS) This bit is set when the GPI3 pin is toggled. 2 EXTSMI2 Toggle Status (XSMI2_STS) This bit is set when the GPI2 pin is toggled. 1 PME# Status (PME_STS) This bit is set when the GPI1 pin is asserted high. 0 EXTSMI# Status (EXT_STS) This bit is set when the EXTSMI# pin is asserted low. Note that the above bits correspond one for one with the bits of the General Purpose SCI Enable and General Purpose SMI Enable registers at offsets 22 and 24: an SCI or SMI is generated if the corresponding bit of the General Purpose SCI or SMI Enable registers, respectively, is set to one. The above bits are set by hardware only and can only be cleared by writing a one to the desired bit. I/O Offset 23-22 - General Purpose SCI Enable ............ RW ........................................always reads 0 15 Reserved 14 Enable SCI on setting of the UW_STS bit .....def=0 ........................................always reads 0 13 Reserved 12 Enable SCI on setting of the BL_STS bit ......def=0 11 Enable SCI on setting of the LID_STS bit .....def=0 10 Enable SCI on setting of the THRM_STS bit def=0 9 Enable SCI on setting of the USB_STS bit ....def=0 8 Enable SCI on setting of the RI_STS bit .......def=0 7 Enable SCI on setting of the XSMI7_STS bit def=0 6 Enable SCI on setting of the XSMI6_STS bit def=0 5 Enable SCI on setting of the XSMI5_STS bit def=0 4 Enable SCI on setting of the XSMI4_STS bit def=0 3 Enable SCI on setting of the XSMI3_STS bit def=0 2 Enable SCI on setting of the XSMI2_STS bit def=0 1 Enable SCI on setting of the PME_STS bit....def=0 0 Enable SCI on setting of the EXT_STS bit ....def=0 These bits allow generation of an SCI using a separate set of conditions from those used for generating an SMI. I/O Offset 25-24 - General Purpose SMI Enable ........... RW ........................................always reads 0 15 Reserved 14 Enable SMI on setting of the UW_STS bit ....def=0 ........................................always reads 0 13 Reserved 12 Enable SMI on setting of the BL_STS bit .....def=0 11 Enable SMI on setting of the LID_STS bit ....def=0 10 Enable SMI on setting of the THRM_STS bit def=0 9 Enable SMI on setting of the USB_STS bit ...def=0 8 Enable SMI on setting of the RI_STS bit ......def=0 7 Enable SMI on setting of the XSMI7_STS bitdef=0 6 Enable SMI on setting of the XSMI6_STS bitdef=0 5 Enable SMI on setting of the XSMI5_STS bitdef=0 4 Enable SMI on setting of the XSMI4_STS bitdef=0 3 Enable SMI on setting of the XSMI3_STS bitdef=0 2 Enable SMI on setting of the XSMI2_STS bitdef=0 1 Enable SMI on setting of the PME_STS bit...def=0 0 Enable SMI on setting of the EXT_STS bit....def=0 These bits allow generation of an SMI using a separate set of conditions from those used for generating an SCI.
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Generic Power Management Registers I/O Offset 29-28 - Global Status .................................... RWC 15 GPIO Range 1 Access Status (GP_R1_STS).. def=0 14 GPIO Range 0 Access Status (GP_R0_STS).. def=0 13 GP3 Timer Timeout Status (GP3_TO_STS).. def=0 12 GP2 Timer Timeout Status (GP3_TO_STS).. def=0 11 SerIRQ SMI Status (SIRQ_SM_STS)............ def=0 ........................................ always reads 0 10-9 Reserved 8 PCKRUN# Resume Status (PR_RSM_STS).. def=0 This bit is set when PCI bus peripherals wake up the system by asserting PCKRUN# 7 Primary IRQ Resume Status (PI_RSM_STS) def=0 This bit is set at the occurrence of primary IRQs as defined in Rx45-44 of PCI configuration space 6 Software SMI Status (SW_SMI_STS)............ def=0 This bit is set when the SMI_CMD port (offset 2F) is written. 5 BIOS Status (BIOS_STS) ................................ def=0 This bit is set when the GBL_RLS bit is set to one (typically by the ACPI software to release control of the SCI/SMI lock). When this bit is reset (by writing a one to this bit position) the GBL_RLS bit is reset at the same time by hardware. 4 Legacy USB Status (LEG_USB_STS) ............ def=0 This bit is set when a legacy USB event occurs. 3 GP1 Timer Time Out Status (GP1_TO_STS) def=0 This bit is set when the GP1 timer times out. GP0 Timer Time Out Status (GP0_TO_STS) def=0 This bit is set when the GP0 timer times out. Secondary Event Timer Time Out Status (ST_TO_STS) ................................................... def=0 This bit is set when the secondary event timer times out. Primary Activity Status (PACT_STS)............ def=0 This bit is set at the occurrence of any enabled primary system activity (see the Primary Activity Detect Status register at offset 30h and the Primary Activity Detect Enable register at offset 34h). After checking this bit, software can check the status bits in the Primary Activity Detect Status register at offset 30h to identify the specific source of the primary event. Note that setting this bit can be enabled to reload the GP0 timer (see bit-0 of the GP Timer Reload Enable register at offset 38). I/O Offset 2B-2A - Global Enable ................................... RW 15 GPIO Range 1 Access Enable (GP_R1_EN) ..def=0 14 GPIO Range 0 Access Enable (GP_R0_EN) ..def=0 13 GP3 Timer Timeout Enable (GP3_TO_EN) ..def=0 12 GP2 Timer Timeout Enable (GP3_TO_EN) ..def=0 11 SerIRQ SMI Enable (SIRQ_SM_EN) ............def=0 ........................................always reads 0 10-9 Reserved 8 PCKRUN# Resume Enable (PR_RSM_EN) ..def=0 This bit may be set to trigger an SMI to be generated when the PR_RSM_STS bit is set. 7 Primary IRQ Resume Enable (PI_RSM_EN) def=0 This bit may be set to trigger an SMI to be generated when the PI_RSM_STS bit is set. 6 Software SMI Enable (SW_SMI_EN) ............def=0 This bit may be set to trigger an SMI to be generated when the SW_SMI_STS bit is set. 5 BIOS Enable (BIOS_EN).................................def=0 This bit may be set to trigger an SMI to be generated when the BIOS_STS bit is set.
4
3
2
2
1
1
0
0
Legacy USB Enable (LEG_USB_EN).............def=0 This bit may be set to trigger an SMI to be generated when the LEG_USB_STS bit is set. GP1 Timer Time Out Enable (GP1_TO_EN) def=0 This bit may be set to trigger an SMI to be generated when the GP1_TO_STS bit is set. GP0 Timer Time Out Enable (GP0_TO_EN) def=0 This bit may be set to trigger an SMI to be generated when the GP0_TO_STS bit is set. Secondary Event Timer Time Out Enable (ST_TO_EN) .....................................................def=0 This bit may be set to trigger an SMI to be generated when the ST_TO_STS bit is set. Primary Activity Enable (PACT_EN) ............def=0 This bit may be set to trigger an SMI to be generated when the PACT_STS bit is set.
Note that SMI can be generated based on the setting of any of the above bits (see the offset 2Ah Global Enable register bit descriptions in the right hand column of this page). The bits in this register are set by hardware only and can only be cleared by writing a one to the desired bit position.
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I/O Offset 2F - SMI Command (SMI_CMD) ................. RW 7-0 SMI Command Writing to this port sets the SW_SMI_STS bit. Note that if the SW_SMI_EN bit is set (see bit-6 of the Global Enable register at offset 2Ah), then an SMI is generated.
I/O Offset 2D-2C - Global Control (GBL_CTL) ............ RW ........................................ always reads 0 15-12 Reserved 11 IDE Secondary Bus Power Off 0 Disable ...................................................default 1 Enable 10 IDE Primary Bus Power Off 0 Disable ...................................................default 1 Enable ........................................ always reads 0 9 Reserved 8 SMI Active (INSMI) 0 SMI Inactive...........................................default 1 SMI Active. If the SMIIG bit is set, this bit needs to be written with a 1 to clear it before the next SMI can be generated. 7 LID Triggering Polarity 0 Rising Edge ............................................default 1 Falling Edge 6 THRM# Triggering Polarity 0 Rising Edge ............................................default 1 Falling Edge 5 Disable Battery Low Resume 0 Enable resume ........................................default 1 Disable resume from suspend when BATLOW# is asserted 4 SMI Lock (SMIIG) 0 Disable SMI Lock 1 Enable SMI Lock (SMI low to gate for the next SMI) ...............................................default 3 Wait for Halt / Stop Grant Cycle for STPCLK# Assertion 0 Don't wait...............................................default 1 Wait This bit works with Rx4C[7] of PCI configuration space to control the start of STPCLK# assertion. 2 Power Button Triggering 0 SCI/SMI generated by PWRBTN# rising edge 1 SCI/SMI generated by PWRBTN# low level Must be set to 1 for ACPI v0.9 compliance. 1 BIOS Release (BIOS_RLS) This bit is set by legacy software to indicate release of the SCI/SMI lock. Upon setting of this bit, hardware automatically sets the GBL_STS bit. This bit is cleared by hardware when the GBL_STS bit cleared by software. Note that if the GBL_EN bit is set (bit-5 of the Power Management Enable register at offset 2), then setting this bit causes an SCI to be generated (because setting this bit causes the GBL_STS bit to be set). 0 SMI Enable (SMI_EN) 0 Disable all SMI generation 1 Enable SMI generation
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I/O Offset 37-34 - Primary Activity Detect Enable ........ RW These bits correspond to the Primary Activity Detect Status bits in offset 33-30. ......................................... always read 0 31-11 Reserved 10 Audio Controller Status Enable ............ (AUD_EN) 0 Don't set PACT_STS if AUD_STS is set .... def 1 Set PACT_STS if AUD_STS is set 9 Keyboard Controller Status Enable ..... (KBC_EN) 0 Don't set PACT_STS if KBC_STS is set..... def 1 Set PACT_STS if KBC_STS is set 8 VGA Status Enable ................................ (VGA_EN) 0 Don't set PACT_STS if VGA_STS is set .... def 1 Set PACT_STS if VGA_STS is set 7 Parallel Port Status Enable ....................(PAR_EN) 0 Don't set PACT_STS if PAR_STS is set ..... def 1 Set PACT_STS if PAR_STS is set 6 Serial Port B Status Enable ................(COMB_EN) 0 Don't set PACT_STS if COMB_STS is set . def 1 Set PACT_STS if COMB_STS is set 5 Serial Port A Status Enable ............... (COMA_EN) 0 Don't set PACT_STS if COMA_STS is set . def 1 Set PACT_STS if COMA_STS is set 4 Floppy Status Enable .............................. (FLP_EN) 0 Don't set PACT_STS if FLP_STS is set ...... def 1 Set PACT_STS if FLP_STS is set 3 Secondary IDE Status Enable ...............(SIDE_EN) 0 Don't set PACT_STS if SIDE_STS is set .... def 1 Set PACT_STS if SIDE_STS is set 2 Primary IDE Status Enable ...................(PIDE_EN) 0 Don't set PACT_STS if PIDE_STS is set.... def 1 Set PACT_STS if PIDE_STS is set 1 Primary INTR Status Enable ............... (PIRQ_EN) 0 Don't set PACT_STS if PIRQ_STS is set.... def 1 Set PACT_STS if PIRQ_STS is set 0 PCI Master Status Enable ..................... (DRQ_EN) 0 Don't set PACT_STS if PCI_STS is set....... def 1 Set PACT_STS if PCI_STS is set Note: Setting of any of the above bits also sets the PACT_STS bit (bit-0 of offset 28) which causes the GP0 timer to be reloaded (if PACT_GP0_EN is set) or generates an SMI (if PACT_EN is set).
I/O Offset 33-30 - Primary Activity Detect Status ....... RWC These bits correspond to the Primary Activity Detect Enable bits in offset 37-34. ..........................................always read 0 31-11 Reserved 10 Audio Controller Access Status ........... (AUD_STS) Set if the audio controller is accessed. Keyboard Controller Access Status..... (KBC_STS) Set if the keyboard controller is accessed via I/O port 60h. 8 VGA Access Status................................ (VGA_STS) Set if the VGA port is accessed via I/O ports 3B03DFh or memory space A0000-BFFFFh. 7 Parallel Port Access Status....................(PAR_STS) Set if the parallel port is accessed via I/.O ports 27827Fh or 378-37Fh (LPT2 or LPT1). 6 Serial Port B Access Status .............. (COMB_STS) Set if serial port B is accessed via I/O ports 2F8-2FFh or 2E8-2EFh. 5 Serial Port A Access Status .............. (COMA_STS) Set if serial port A is accessed via I/O ports 3F8-3FFh or 3E8-3EFh. 4 Floppy Access Status.............................. (FLP_STS) Set if the floppy devices are accessed via I/O ports 3F0-3F5h or 3F7h. 3 Secondary IDE Access Status...............(SIDE_STS) Set if the secondary IDE port is accessed via I/O ports 170-177h or 376h. 2 Primary IDE Access Status ................. (PIDE_STS) Set if the primary IDE port is accessed via I/O ports 1F0-1F7h or 3F6h. 1 Primary Interrupt Activity Status...... (PIRQ_STS) Set on the occurrence of a primary interrupt (enabled via the "Primary Interrupt Channel" register at Function 3 PCI configuration register offset 44h). 0 PCI Master Activity Status .................... (PCI_STS) Set on the occurrence of PCI master activity. Note: The bits above correspond to the bits of the Primary Activity Detect Enable register at offset 34 (see right hand column of this page): if the corresponding bit is set in that register, setting of the above bits will cause the PACT_STS bit to be set (bit-0 of the Global Status register at offset 28). Setting of PACT_STS may be set up to enable a "Primary Activity Event": an SMI will be generated if PACT_EN is set (bit-0 of the Global Enable register at offset 2Ah) and/or the GP0 timer will be reloaded if the "GP0 Timer Reload on Primary Activity" bit is set (bit-0 of the GP Timer Reload Enable register at offset 38 on this page). Note: Bits above also correspond to bits of the GP Timer Reload Enable register at offset 38: if the corresponding bit is set in that register, setting the bit in this register will cause the indicated timer to be reloaded. Bits in this register are set by hardware only and may only be cleared by writing a 1 to the desired bit. All bits default to 0. Revision 0.3 June 17, 1999 9
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General Purpose I/O Registers I/O Offset 45-44 - External SMI Input Value (EXTSMI_VAL) ................................................................ RO Depending on the configuration, up to 8 external SCI/SMI ports are available as indicated below. The state of these inputs may be read in this register. 15-11 10 9 8 7 6 5 4 3 2 1 0 ........................................always reads 0 Reserved Hardware Monitor IRQ Status SMBus IRQ Status SMBus Resume Status RI# (GPI12 Pin) Input Value SMBALRT# (GPI11 Pin) Input Value ........................................always reads 0 Reserved SLPBTN# (GPI13 Pin) Input Value LID (GPI10 Pin) Input Value BATLOW# (GPI9 Pin) Input Value PME# (GPI1 Pin) Input Value EXTSMI# Input Value
I/O Offset 3B-38 - GP Timer Reload Enable .................. RW All bits in this register default to 0 on power up. ..........................................always read 0 31-11 Reserved 7 Enable GP1 Timer Reload on KBC Access 1 = setting of KBC_STS causes GP1 timer to reload. 6 Enable GP1 Timer Reload on Serial Port Access 1 = setting of COMA_STS or COMB_STScauses GP1 timer to reload. ..........................................always read 0 5 Reserved 4 Enable GP1 Timer Reload on VGA Access 1 = setting of VGA_STS causes GP1 timer to reload. 3 Enable GP1 Timer Reload on IDE/Floppy Access 1 = setting of FLP_STS, PIDE_STS, or SIDE_STS causes GP1 timer to reload. 2 Ena GP3 Timer Reload on GPIO Range 1 Access 1 = setting of GR1_STS causes GP3 timer to reload. 1 Ena GP2 Timer Reload on GPIO Range 0 Access 1 = setting of GR0_STS causes GP2 timer to reload. 0 Enable GP0 Timer Reload on Primary Activity 1 = setting of PACT_STS causes GP0 timer to reload. Primary activities are enabled via the Primary Activity Detect Enable register (offset 37-34) with status recorded in the Primary Activity Detect Status register (offset 33-30).
I/O Offset 4B-48 - GPI Port Input Value (GPI_VAL) .... RO ......................................... always read 0 31-22 Reserved 21-0 GPI[21-0] Input Value ............................. Read Only I/O Offset 4F-4C - GPO Port Output Value (GPO_VAL)RW Reads from this register return the last value written (held on chip) ........................................always reads 0 31 Reserved 30-0 GPO[30-0] Output Value..........default = 7FFFFFFh
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Function 3 Registers - Power Management and SMBus
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Processor Bus States The VT82C596B supports the complete set of C0 to C3 processor states as specified in the Advanced Configuration and Power Interface (ACPI) specification (and defined in ACPI I/O space Registers 10-15): C0: C1: C2: Normal Operation CPU Halt (controlled by software). Stop Clock. Entered when the P_LVL2 register is read. The STPCLK# signal is asserted to put the processor in the Stop Grant State. If the SRAM_ZZ bit is set to 1, then the ZZ pin is also asserted (after the acknowledgement of the stop grant bus cycle) for powering down the cache SRAM. The CPUSTP# signal is not asserted so that host clocks remain running. To exit this state, the chip negates the ZZ signal and then negates STPCLK#. Suspend. Entered when the P_LVL3 register is read. In addition to STPCLK# and ZZ assertion as in the C2 state, the SUSST1# (suspend status 1) signal is asserted to tell the north bridge to switch to "Suspend DRAM Refresh" mode based on the 32KHz suspend clock (SUSCLK) provided by the VT82C596B. If the HOST_STP bit is enabled, then CPUSTP# is also asserted to stop clock generation and put the CPU into Stop Clock State. To exit this state, the chip negates CPUSTP# and allows time for the processor PLL to lock. Then the SUSST1#, ZZ, and STPCLK# signals are negated to resume to normal operation.
FUNCTIONAL DESCRIPTIONS
Power Management
Power Management Subsystem Overview The power management function of the VT82C596B is indicated in the following block diagram:
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During normal operation, two mechanisms are provided to modulate CPU execution and control power consumption by throttling the duty cycle of STPCLK#: a. b. Setting the THT_EN bit to 1, the duty cycle defined in THT_DTY (IO space Rx10) is used. THRM# pin assertion enables automatic clock throttling with duty cycle pre-configured in THM_DTY (PCI configuration Rx4C).
Figure 6. Power Management Subsystem Block Diagram Refer to ACPI Specification v1.0 and APM specification v1.2 for additional information.
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Functional Descriptions
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SUSC#) are provided to turn off more system power planes as the system moves to deeper power-down states, i.e., from normal operation to POS (only SUSA# asserted), to STR (both SUSA# and SUSB# asserted), and to STD (all three SUS# signals asserted). In particular, the assertion of SUSC# can be used to turn off the VCC supply to the VT82C596B. Two suspend status indicators (SUSST1-2#) are provided to inform the north bridge and the rest of the system of the processor and system suspend states. SUSST2# is asserted when the system enters any suspend state. SUSST1# is asserted when the system enters the suspend state or the processor enters the C3 state. SUSST1# is connected to the north bridge to switch between normal and suspend-DRAMrefresh modes. General Purpose I/O Ports As ACPI compliant hardware, the VT82C596B includes PWRBTN#, SLPBTN#, and RI# pins to implement power button, sleep button, and ring indicator functionality, respectively. Furthermore, the VT82C596B offers many general-purpose I/O ports with the following capabilities: I2C/SMB Support Thermal Detect Notebook Lid Open/Close Detect Battery Low Detect Twenty-two General Purpose Input Ports (10 dedicated and 12 multiplexed with other functions). * Thirty-one General Purpose Output Ports (6 dedicated and 25 multiplexed with other functions) In addition, the VT82C596B provides eight external SMI pins (one dedicated EXTSMI# pin and seven pins shared with general purpose input pins). Once enabled, each of the external SMI inputs triggers an SCI or SMI at both the rising and falling edges of the corresponding input signal. Software can check the status of the input pins and take appropriate actions. * * * * *
System Suspend States and Power Plane Control There are three power planes inside the VT82C596B. The first power plane (VCCSUS) is always on unless turned off by the mechanical switch. The second power plane (VCC) is controlled by chip output SUSC# (also called "PSON"). The third plane (VCCRTC) is powered by the combination of the VCCSUS and the external battery (VBAT) for the integrated real time clock. Most of the circuitry inside the VT82C596B is powered by VCC. The amount of logic powered by VCCSUS is very small; its main function is to control the supply of VCC and other power planes. VCCRTC is always on unless both the mechanical switch and VBAT are removed. The VT82C596B supports multiple system suspend states by configuring the SLP_TYP field of ACPI I/O space register Rx4-5: a) POS (Power On Suspend): Most devices in the system remain powered. The host bus is put into an equivalent of the C3 state. In particular, the CPU is put into the Stop Grant State or Stop Clock State depending on the setting of the HOST_STP bit. SUSST1# is asserted to tell the north bridge to switch to "Suspend DRAM Refresh" mode based on the 32KHz SUSCLK provided by the VT82C596B. As to the PCI bus, setting the PCLK_RUN bit to 0 enables the CLKRUN protocol defined in the PCI Mobile Design Guide. That is, the PCKRUN# pin will be de-activated after the PCI bus is idle for 26 clocks. Any PCI bus masters including the north bridge may resume PCI clock operation by pulling the PCKRUN# pin low. During the PCKRUN# deactivation period, the PCISTP# pin may be activated to disable the output of the PCI clock generator if the PCI_STP bit is enabled. When the system resumes from POS, the VT82C496 can optionally resume without resetting the system, can reset the processor only, or can reset the entire system. When no reset is performed, the chip only needs to wait for the clock synthesizer and processor PLL to lock before the system is resumed, which typically takes 20ms. STR (Suspend to DRAM): Power is removed from most of the system except the system DRAM. Power is supplied to the suspend refresh logic in the north bridge (VTT of VT82C598AT) and the suspend logic of the VT82C596B (VCCSUS). The VT82C596B provides a 32KHz suspend clock to the north bridge for it to use to continue DRAM refresh. STD (Suspend to Disk, also called Soft-off): Power is removed from most of the system except the suspend logic of VT82C596B (VCCSUS). Mechanical Off: This is not a suspend state. All power in the system is removed except the RTC battery.
b)
c)
d)
The suspend state is entered by setting the SLP_EN bit to 1. Three power plane control signals (SUSA#, SUSB# and
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Functional Descriptions
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3) Generic Global Events defined in the GBL_STS and GBL_EN registers. These registers are mainly used for SMI: * * * * * PCI Bus Clock Run Resume Primary Interrupt Occurance GP0 and GP1 Timer Time Out Secondary Event Timer Time Out Occurrence of Primary Events (defined in register PACT_STS and PACT_EN) * Legacy USB accesses (keyboard and mouse) - Software SMI System and Processor Resume Events Depending on the system suspend state, different features can be enabled to resume the system. There are two classes of resume events: a) VCCSUS-based events. Event logic resides in the VCCSUS plane and thus can resume the system from any suspend state. Such events include PWRBTN#, RI#, BATLOW#, LID, SMBus resume event, RTC alarm, EXTSMI#, and GP1 (EXTSMI1#). VCC-Based Events. Event logic resides in the VCC plane and thus can only resume the system from the POS state. Such events include the ACPI PM timer, USB resume, and EXTSMI2-7#.
Power Management Events Three types of power management events are supported: 1) ACPI-required Fixed Events defined in the PM1a_STS and PM1a_EN registers. These events can trigger either SCI or SMI depending on the SCI_EN bit: * * * * * PWRBTN# Triggering RTC Alarm Sleep Button ACPI Power Management Timer Carry (always SCI) BIOS Release (always SCI)
2) ACPI-aware General Purpose Function Events defined in the GP_STS and GP_SCI_EN, and GP_SMI_EN registers. These events can trigger either SCI or SMI depending on the setting of individual SMI and SCI enable bits: * * * * * * External SMI triggering USB Resume Ring Indicator (RI#) Battery Low Detect (BATLOW#) Notebook Lid Open/Close Detect (LID) Thermal Detect (THRM#)
b)
Skt-7 or Slot-1 Host CPU
SMIACT#
HCLK SMI# / STPCLK#
CPU Bus
ZZ
3D Graphics Controller
GCLK
L2 Cache (Socket-7) PC100 SDRAM
AGP Bus
GCKRUN#
PCKRUN# PCLK
VT82C598MVP Apollo MVP3 or VT82C693 Apollo ProPlus
SUSCLK, SUSST1#
Memory Bus
CKE# HCLK GCLK PCLK Module ID
PCI Bus ISA IDE BIOS ROM USB Keyboard / Mouse
MCLK CPUSTP# PCISTP#
VT82C596B 324 BGA
SMBus
Clock Generator GPIO and ACPI Events Power Plane & Peripheral Control
Figure 7. Apollo MVP3 System Block Diagram Using the VT82C596B South Bridge
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Functional Descriptions
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enabled, the occurrence of the primary event reloads the GP0 timer if the PACT_GP0_EN bit is also set to 1. The cause of the timer reload is recorded in the corresponding bit of PRI_ACT_STS register while the timer is reloaded. If no enabled primary event occurs during the count down, the GP0 timer will time out (count down to 0) and the system can be programmed (setting the GP0TO_EN bit in the GBL_EN register to one) to trigger an SMI to switch the system to a power down mode. The VT82C596B distinguishes two kinds of interrupt requests as far as power management is concerned: the primary and secondary interrupts. Like other primary events, the occurrence of a primary interrupt demands that the system be restored to full processing capability. Secondary interrupts, however, are typically used for housekeeping tasks in the background unnoticeable to the user. The VT82C596B allows each channel of interrupt request to be declared as either primary, secondary, or ignorable in the PIRQ_CH and SIRQ_CH registers. Secondary interrupts are the only system secondary events defined in the VT82C596B. Like primary events, primary interrupts can be made to reload the GP0 timer by setting the PIRQ_EN bit to 1. Secondary interrupts do not reload the GP0 timer. Therefore the GP0 timer will time out and the SMI routine can put the system into power down mode if no events other than secondary interrupts are happening periodically in the background. Primary events can be programmed to trigger an SMI (setting of the PACT_EN bit). Typically, this SMI triggering is turned off during normal system operation to avoid degrading system performance. Triggering is turned on by the SMI routine before entering the power down mode so that the system may be returned to normal operation at the occurrence of primary events. At the same time, the GP0 timer is reloaded and the count down process is restarted. Peripheral Events Primary and secondary events define system events in general and the response is typically expressed in terms of system events. Individual peripheral events can also be monitored by the VT82C596B through the GP1 timer. The following four categories of peripheral events are distinguished (via register GP_RLD_EN): Bit-7 Keyboard Access Bit-6 Serial Port Access Bit-4 Video Access Bit-3 IDE/Floppy Access The four categories are subsets of the primary events as defined in PRI_ACT_EN and the occurrence of these events can be checked through a common register PRI_ACT_STS. As a peripheral timer, GP1 can be used to monitor one (or more than one) of the above four device types by programming the corresponding bit to one and the other bits to zero. Time out of the GP1 timer indicates no activity of the corresponding device type and appropriate action can be taken as a result.
Legacy Power Management Timers In addition to the ACPI power management timer, the VT82C596B includes the following four legacy power management timers: GP0 Timer: general purpose timer with primary event GP1 Timer: general purpose timer with peripheral event reload Secondary Event Timer: to monitor secondary events Conserve Mode Timer: Hardware-controlled return to standby The normal sequence of operations for a general purpose timer (GP0 or GP1) is to 1) First program the time base and timer value of the initial count (register GP_TIM_CNT). 2) Then activate counting by setting the GP0_START or GP1_START bit to one: the timer will start with the initial count and count down towards 0. 3) When the timer counts down to zero, an SMI will be generated if enabled (GP0TO_EN and GP1TO_EN in the GBL_EN register) with status recorded (GP0TO_STS and GP1TO_STS in the GBL_STS register). 4) Each timer can also be programmed to reload the initial count and restart counting automatically after counting down to 0. This feature is not used in standard VIA BIOS. The GP0 and GP1 timers can be used just as the general purpose timers described above. However, they can also be programmed to reload the initial count by system primary events or peripheral events thus used as primary event (global standby) timer and peripheral timer, respectively. The secondary event timer is solely used to monitor secondary events. System Primary and Secondary Events Primary system events are distinguished in the PRI_ACT_STS and PRI_ACT_EN registers: Trigger I/O port 60h I/O ports 3F8h-3FFh, 2F8h-2FFh, 3E8h-3EFh, or 2E8h-2EFh 5 Parallel Port Access I/O ports 378h-37Fh or 278h-27Fh 4 Video Access I/O ports 3B0h-3DFh or memory A/B segments 3 IDE/Floppy Access I/O ports 1F0h-1F7h, 170h-177h, or 3F5h 2 Reserved 1 Primary Interrupts Each channel of the interrupt controller can be programmed to be a primary or secondary interrupt 0 ISA Master/DMA Activity Each category can be enabled as a primary event by setting the corresponding bit of the PRI_ACT_EN register to 1. If Bit Event 7 Keyboard Access 6 Serial Port Access
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Functional Descriptions
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ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings Parameter
Ambient operating temperature Storage temperature Input voltage Output voltage (VCC = 5V) Output voltage (VCC = 3.1 - 3.6V)
Min
0 -55 -0.5 -0.5 -0.5
Max
70 125 5.5 5.5 VCC + 0.5
Unit
oC oC Volts Volts Volts
Note: Stress above the conditions listed may cause permanent damage to the device. Functional operation of this device should be restricted to the conditions described under operating conditions.
DC Characteristics
TA-0-70oC, VCC=5V+/-5%, GND=0V
Symbol
VIL VIH VOL VOH IIL IOZ ICC
Parameter
Input low voltage Input high voltage Output low voltage Output high voltage Input leakage current Tristate leakage current Power supply current
Min
-0.50 2.0 2.4 -
Max
0.8 VCC+0.5 0.45 +/-10 +/-20 80
Unit
V V V V uA uA mA
Condition
IOL=4.0mA IOH=-1.0mA 0Revision 0.3 June 17, 1999
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Electrical Specifications
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AC Timing Specifications
Table 6. AC Characteristics - PCI Cycle Timing
Parameter TS TS TS TS TH TH TH TH TVD TVD TVD TVD TVD TFD TFD AD[31:0] Setup Time to PCLK Rising FRAME#,TRDY#,IRDY# Setup Time to PCLK Rising CBE[3:0]#, STOP#,DEVSEL# Setup Time to PCLK Rising PGNT# Setup Time to PCLK Rising AD[31:0] Hold Time from PCLK Rising FRAME#,TRDY#,IRDY# Hold Time from PCLK Rising CBE[3:0]#, STOP#,DEVSEL# Hold Time from PCLK Rising PGNT# Hold Time from PCLK Rising AD[31:0] Valid Delay from PCLK Rising (address phase) AD[31:0] Valid Delay from PCLK Rising (data phase) FRAME#,TRDY#,IRDY# Valid Delay from PCLK Rising CBE[3:0]#, STOP#,DEVSEL# Valid Delay from PCLK Rising PREQ# Valid Delay from PCLK Rising FRAME#,TRDY#,IRDY# Float Delay from PCLK Rising CBE[3:0]#, STOP#,DEVSEL# Float Delay from PCLK Rising Min 7 7 7 12 0 0 0 0 2 2 2 2 2 11 11 11 11 12 28 28 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0pf on min, 50pf on max 0pf on min, 50pf on max 0pf on min, 50pf on max 0pf on min, 50pf on max 0pf on min, 50pf on max 0pf on min, 50pf on max 0pf on min, 50pf on max Notes
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Table 7. AC Characteristics - UltraDMA-33 IDE Bus Interface Timing
Symbol TENV1 TDS1 TDH1 TENV2 TDVS2 TDVH2 TDVS2 TDVH2 TRFS TRP TLI4 TLI4 TZA4 TDVS4 TDVH4 TLI5 TLI5 TMIL5 TDVS5 TDVH5 TMIL6 TZA6 TLI5 TMIL5 T2 T3 T4 T5 TWDS TWDH TRDS TRDH
Description Envelope time for read initial Data setup time for read initial Data hold time for read initial (rise) Envelope time for write initial (rise) Data setup time for write initial (fall) Data hold time for write initial (fall) Data setup time for write initial Data hold time for write initial READY to final STROBE time READY to Pause time Limited interlock time (to STOP) Limited interlock time (to Host DMARDY) Delay time required for output drives turning on Data setup time for read terminating Data hold time for read terminating Limited interlock time (to STOP) Limited interlock time (to Host STROBE) Limited interlock time with minimum Data setup time for write terminating Data hold time for write terminating Limited interlock time with minimum Delay time required for output drives turning on Limited interlock time Limited interlock time with minimum Delay time of PCLK to DCS3,1# Delay time of PCLK to DA[2:0] Delay time of PCLK to DIOW# Delay time of PCLK to DIOR# Data setup time during PIO write Data hold time during PIO write Data setup time during PIO read Data hold time during PIO read
Timing 29.3 1.1 2.3 29.3 42.2 17.8 42.0 17.2 21.3 180.0 95.1 125.3 102.0 55.3 31.6 125.3 95.2 120.6 57.7 31.8 155.8 68.5 65.2 90.6 4.8 5.3 9.3 9.2 85.5 31.7 0.4 2.1
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Electrical Specifications
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DDRQ (Drive) DDACK# (Host) STOP (Host) HDMARDY# (Host)
TUI
TENV1 DSTROBE (Drive) Data
TLI1 TDS1
TDH1
Figure 8. UltraDMA-33 IDE Timing - Drive Initiating DMA Burst for Read Command
DDRQ (Drive) DDACK# (Host) STOP (Host) DDMARDY# (Drive)
TUI TENV2
TUI HSTROBE (Host) DDMARDY# (Drive) HSTROBE (Host) Data TDVS2 TDVH2
Figure 9. UltraDMA-33 IDE Timing - Drive Initiating Burst for Write Command
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Electrical Specifications
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DDRQ (Drive) DDACK# (Host) For Write: DDMARDY# (Drive) TRFS HSTROBE (Host) For Read: STOP (Host) HDMARDY# (Host)
TRP
Figure 10. UltraDMA-33 IDE Timing - Pausing a DMA Burst
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Electrical Specifications
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DDRQ (Drive) DDACK# (Host) TLI4 STOP (Host) HDMARDY# (Host) Data TZA4
CRC
TDVS4
TDVH4
Figure 11. UltraDMA-33 IDE Timing - Drive Terminating DMA Burst During Read Command
DDRQ (Drive) DDACK# (Host) STOP (Host) DDMARDY# (Host) HSTROBE (Host) TLI5B Data
CRC
TLI5A
TMLI5
TDVS5
TDVH5
Figure 12. UltraDMA-33 IDE Timing - Drive Terminating DMA Burst During Write Command
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Electrical Specifications
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TMLI6 DDRQ# (Drive) DDACK# (Host) STOP (Host) HDMARDY# (Host) Data
CRC
TZA6
Figure 13. UltraDMA-33 IDE Timing - Host Terminating DMA Burst During Read Command
DDRQ (Drive) DDACK# (Host) TMIL7 STOP (Host) HSTROBE# (Host) Data TLI7 TDVS7
CRC
TDVH7
Figure 14. UltraDMA-33 IDE Timing - Host Terminating DMA Burst During Write Command
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Electrical Specifications
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T2 DCS3# / DCS1# DA [2:0] T3 DIOW# DD Write TWDS T5 DIOR# DD Read TRDS TRDH TWDH T4
Figure 15. UltraDMA-33 IDE Timing - PIO Cycle
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Electrical Specifications
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PACKAGE MECHANICAL SPECIFICATIONS
Pin #1 Corner
O 1.00 (3X) Ref.
Y W V R L
= Date Code Year = Date Code Week = Chip Version = Revision Code = Lot Code
<<::997$,:$1 //5//////
24.00 Ref.
o0.750.15(324X) o0.10 S C o0.30 S C A S B S
Reference Document: JEDEC Spec MO-151
Figure 16. Mechanical Specifications - 324-Pin Ball Grid Array Package
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4.00*45(4X)
97&%
24.00 Ref.
Package Mechanical Specifications

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